From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933101AbbLHHRO (ORCPT ); Tue, 8 Dec 2015 02:17:14 -0500 Received: from mailout4.w1.samsung.com ([210.118.77.14]:47948 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932631AbbLHHRM (ORCPT ); Tue, 8 Dec 2015 02:17:12 -0500 X-AuditID: cbfec7f4-f79026d00000418a-62-566683f451dd Subject: Re: [PATCH v4 3/8] ARM: dts: Exynos5420: add CPU OPP properties To: Bartlomiej Zolnierkiewicz , Thomas Abraham , Sylwester Nawrocki , Kukjin Kim , Kukjin Kim , Viresh Kumar , Ben Gamari References: <1449512300-17230-1-git-send-email-b.zolnierkie@samsung.com> <1449512300-17230-4-git-send-email-b.zolnierkie@samsung.com> Cc: Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , Tobias Jakobi , Anand Moon , linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Doug Anderson , Andreas Faerber From: Krzysztof Kozlowski X-Enigmail-Draft-Status: N1110 Message-id: <566683EC.9050806@samsung.com> Date: Tue, 08 Dec 2015 16:17:00 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-version: 1.0 In-reply-to: <1449512300-17230-4-git-send-email-b.zolnierkie@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNIsWRmVeSWpSXmKPExsVy+t/xq7pfmtPCDC4t1bdo3lRssXHGelaL WfPvslhc//Kc1eLssoNsFv8fvWa1ePN2DZPF6xeGFr0LrrJZ9D9+zWzx9fAKRos3DzczWmx6 fI3V4vKuOWwWn3uPMFrMOL+PyWLdxlvsFofftLNadCxjtGhb/YHVYtWuP4wWG796OIh5zG64 yOKxc9Zddo9NqzrZPO5c28PmsXlJvce/Y+weW/qBwn1bVjF6nPnt7LH92jxmj82nqz0+b5IL 4InisklJzcksSy3St0vgyvi0pLhgg3HF+5ddTA2ML9W6GDk5JARMJGZ/+cwEYYtJXLi3nq2L kYtDSGApo0TT28nsEM4vRolP16aCVQkLeEi8ffAWLCEisJhJou/FB6iqdkaJ5o7jYP3MAvNY JDZ3nAZrYRMwlti8fAkbxBI5id7uSSwgNq+AlkTPge9ANgcHi4CqxKvNmiCmqECExKIdmRAV ghI/Jt8Dq+AU8JRY0JwEYjIL6Encv6gFUsEsIC+xec1b5gmMgrOQNMxCqJqFpGoBI/MqRtHU 0uSC4qT0XEO94sTc4tK8dL3k/NxNjJAo/rKDcfExq0OMAhyMSjy8J46lhgmxJpYVV+YeYpTg YFYS4W3VTQsT4k1JrKxKLcqPLyrNSS0+xCjNwaIkzjt31/sQIYH0xJLU7NTUgtQimCwTB6dU A6PENaeC92un7VS97vhKM1zlju8rswkNvR88RDLeCsU6z6udw2/zZIbkLmm1bct/3vp74kFz wJcD29Tqtfe93z+rsXif2PQ1pS+vLD5WpfzW6MEJ3m1Ma/RuLZ8hW1Cjdf/vgo3BHyWN1H5s 3LPs5GfVe2GWF1Rmrio68MMuyin/Hdu198/MzCJjlFiKMxINtZiLihMBg/w4Yt4CAAA= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote: > From: Thomas Abraham > > For Exynos5420 platforms, add CPU operating points for > migrating from Exynos specific cpufreq driver to using > generic cpufreq driver. > > Changes by Bartlomiej: > - split Exynos5420 support from the original patch > > Changes by Ben Gamari: > - Port to operating-points-v2 > > Cc: Kukjin Kim > Cc: Doug Anderson > Cc: Javier Martinez Canillas > Cc: Andreas Faerber > Cc: Sachin Kamat Sachin's address does not work neither. > Cc: Thomas Abraham Thomas' SoB disappeared. I see that you directly re-used Thomas' values for voltages and frequencies. For Exynos5420 we could go down to 200 MHz (for both cores) but this can be fine-tuned per-board later. Best regards, Krzysztof > Signed-off-by: Ben Gamari > Signed-off-by: Bartlomiej Zolnierkiewicz > --- > arch/arm/boot/dts/exynos5420.dtsi | 122 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 122 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi > index 48a0a55..f8f70a5 100644 > --- a/arch/arm/boot/dts/exynos5420.dtsi > +++ b/arch/arm/boot/dts/exynos5420.dtsi > @@ -50,6 +50,116 @@ > usbdrdphy1 = &usbdrd_phy1; > }; > > + cpu0_opp_table: opp_table0 { > + compatible = "operating-points-v2"; > + opp-shared; > + opp00@1800000000 { > + opp-hz = /bits/ 64 <1800000000>; > + opp-microvolt = <1250000>; > + clock-latency-ns = <140000>; > + }; > + opp01@1700000000 { > + opp-hz = /bits/ 64 <1700000000>; > + opp-microvolt = <1212500>; > + clock-latency-ns = <140000>; > + }; > + opp02@1600000000 { > + opp-hz = /bits/ 64 <1600000000>; > + opp-microvolt = <1175000>; > + clock-latency-ns = <140000>; > + }; > + opp03@1500000000 { > + opp-hz = /bits/ 64 <1500000000>; > + opp-microvolt = <1137500>; > + clock-latency-ns = <140000>; > + }; > + opp04@1400000000 { > + opp-hz = /bits/ 64 <1400000000>; > + opp-microvolt = <1112500>; > + clock-latency-ns = <140000>; > + }; > + opp05@1300000000 { > + opp-hz = /bits/ 64 <1300000000>; > + opp-microvolt = <1062500>; > + clock-latency-ns = <140000>; > + }; > + opp06@1200000000 { > + opp-hz = /bits/ 64 <1200000000>; > + opp-microvolt = <1037500>; > + clock-latency-ns = <140000>; > + }; > + opp07@1100000000 { > + opp-hz = /bits/ 64 <1100000000>; > + opp-microvolt = <1012500>; > + clock-latency-ns = <140000>; > + }; > + opp08@1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = < 987500>; > + clock-latency-ns = <140000>; > + }; > + opp09@900000000 { > + opp-hz = /bits/ 64 <900000000>; > + opp-microvolt = < 962500>; > + clock-latency-ns = <140000>; > + }; > + opp10@800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-microvolt = < 937500>; > + clock-latency-ns = <140000>; > + }; > + opp11@700000000 { > + opp-hz = /bits/ 64 <700000000>; > + opp-microvolt = < 912500>; > + clock-latency-ns = <140000>; > + }; > + }; > + > + cpu1_opp_table: opp_table1 { > + compatible = "operating-points-v2"; > + opp-shared; > + opp00@1300000000 { > + opp-hz = /bits/ 64 <1300000000>; > + opp-microvolt = <1275000>; > + clock-latency-ns = <140000>; > + }; > + opp01@1200000000 { > + opp-hz = /bits/ 64 <1200000000>; > + opp-microvolt = <1212500>; > + clock-latency-ns = <140000>; > + }; > + opp02@1100000000 { > + opp-hz = /bits/ 64 <1100000000>; > + opp-microvolt = <1162500>; > + clock-latency-ns = <140000>; > + }; > + opp03@1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = <1112500>; > + clock-latency-ns = <140000>; > + }; > + opp04@900000000 { > + opp-hz = /bits/ 64 <900000000>; > + opp-microvolt = <1062500>; > + clock-latency-ns = <140000>; > + }; > + opp05@800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-microvolt = <1025000>; > + clock-latency-ns = <140000>; > + }; > + opp06@700000000 { > + opp-hz = /bits/ 64 <700000000>; > + opp-microvolt = <975000>; > + clock-latency-ns = <140000>; > + }; > + opp07@600000000 { > + opp-hz = /bits/ 64 <600000000>; > + opp-microvolt = <937500>; > + clock-latency-ns = <140000>; > + }; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -58,8 +168,11 @@ > device_type = "cpu"; > compatible = "arm,cortex-a15"; > reg = <0x0>; > + clocks = <&clock CLK_ARM_CLK>; > + clock-names = "cpu-cluster.0"; > clock-frequency = <1800000000>; > cci-control-port = <&cci_control1>; > + operating-points-v2 = <&cpu0_opp_table>; > }; > > cpu1: cpu@1 { > @@ -68,6 +181,7 @@ > reg = <0x1>; > clock-frequency = <1800000000>; > cci-control-port = <&cci_control1>; > + operating-points-v2 = <&cpu0_opp_table>; > }; > > cpu2: cpu@2 { > @@ -76,6 +190,7 @@ > reg = <0x2>; > clock-frequency = <1800000000>; > cci-control-port = <&cci_control1>; > + operating-points-v2 = <&cpu0_opp_table>; > }; > > cpu3: cpu@3 { > @@ -84,14 +199,18 @@ > reg = <0x3>; > clock-frequency = <1800000000>; > cci-control-port = <&cci_control1>; > + operating-points-v2 = <&cpu0_opp_table>; > }; > > cpu4: cpu@100 { > device_type = "cpu"; > compatible = "arm,cortex-a7"; > reg = <0x100>; > + clocks = <&clock CLK_KFC_CLK>; > + clock-names = "cpu-cluster.1"; > clock-frequency = <1000000000>; > cci-control-port = <&cci_control0>; > + operating-points-v2 = <&cpu1_opp_table>; > }; > > cpu5: cpu@101 { > @@ -100,6 +219,7 @@ > reg = <0x101>; > clock-frequency = <1000000000>; > cci-control-port = <&cci_control0>; > + operating-points-v2 = <&cpu1_opp_table>; > }; > > cpu6: cpu@102 { > @@ -108,6 +228,7 @@ > reg = <0x102>; > clock-frequency = <1000000000>; > cci-control-port = <&cci_control0>; > + operating-points-v2 = <&cpu1_opp_table>; > }; > > cpu7: cpu@103 { > @@ -116,6 +237,7 @@ > reg = <0x103>; > clock-frequency = <1000000000>; > cci-control-port = <&cci_control0>; > + operating-points-v2 = <&cpu1_opp_table>; > }; > }; > >