From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933322AbbLHINm (ORCPT ); Tue, 8 Dec 2015 03:13:42 -0500 Received: from mailout1.w1.samsung.com ([210.118.77.11]:54585 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932837AbbLHINi (ORCPT ); Tue, 8 Dec 2015 03:13:38 -0500 X-AuditID: cbfec7f5-f79b16d000005389-39-5666912fec8a Subject: Re: [PATCH v4 7/8] ARM: dts: Exynos5422: fix OPP tables To: Bartlomiej Zolnierkiewicz , Thomas Abraham , Sylwester Nawrocki , Mike Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar , Ben Gamari References: <1449512300-17230-1-git-send-email-b.zolnierkie@samsung.com> <1449512300-17230-8-git-send-email-b.zolnierkie@samsung.com> Cc: Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , Tobias Jakobi , Anand Moon , linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org From: Krzysztof Kozlowski X-Enigmail-Draft-Status: N1110 Message-id: <56669126.7050803@samsung.com> Date: Tue, 08 Dec 2015 17:13:26 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-version: 1.0 In-reply-to: <1449512300-17230-8-git-send-email-b.zolnierkie@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHIsWRmVeSWpSXmKPExsVy+t/xy7r6E9PCDGadk7TYOGM9q8Ws+XdZ LK5/ec5q8f/Ra1aLN2/XMFm8fmFo0bvgKptF/+PXzBZfD69gtHjzcDOjxabH11gtLu+aw2bx ufcIo8WM8/uYLNZtvMVu8XTCRTaLw2/aWS06ljFatK3+wGqxatcfRouNXz0cRD12zrrL7rFp VSebx51re9g8Ni+p9/h3jN1jSz9QuG/LKkaPM7+dPbZfm8fs8XmTXABXFJdNSmpOZllqkb5d AlfGlIMaBdckK+Yv8GxgXCXSxcjJISFgIvG5YS4ThC0mceHeerYuRi4OIYGljBKNa3czQzi/ GCXebHzECFIlLOAgsXHHNhaQhIjAWSaJuTOeQLW0M0qce3WHCcRhFrjILLFiRh/YYDYBY4nN y5ewQSyRk+jtngTUzsHBK6AlceSpF0iYRUBV4v3lI2BhUYEIiUU7MkHCvAKCEj8m32MBsTkF PCU290xiBilhFtCTuH9RCyTMLCAvsXnNW+YJjIKzkHTMQqiahaRqASPzKkbR1NLkguKk9Fwj veLE3OLSvHS95PzcTYyQWP26g3HpMatDjAIcjEo8vAonU8OEWBPLiitzDzFKcDArifC26qaF CfGmJFZWpRblxxeV5qQWH2KU5mBREueduet9iJBAemJJanZqakFqEUyWiYNTqoFRcdbNdbeE eUNE+rWmFx9fphnb1NkhKNCka8rfcp1vyvu5hRqvVtkGJ/31fG/qM8Hr8geRS4unN7q/+Shz Qa5V747byb8xvPIe2RcDDhw+W7mY9yfv7R/fK1Ib87/NEdoy54uE0EW1TV/KV5wIv3+Hp9f1 lNMjE441z6xaz/em7S08mOCgtGeBEktxRqKhFnNRcSIA3ojj2tECAAA= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08.12.2015 03:18, Bartlomiej Zolnierkiewicz wrote: > From: Ben Gamari > > The Exynos 5422 is identical to the 5800 except for the fact that it > boots from the A7 cores. Consequently, the core numbering is different: > cores 0-3 are A7s whereas 4-7 are A15s. > > We can reuse the device tree of the 5800 for the 5422 but we must take > care to override the OPP tables and CPU clocks. These are otherwise > inherited from the exynos5800 devicetree, which has the CPU clusters > reversed compared to the 5422. This results in the A15 cores only > reaching 1.4GHz, the maximum rate of the KFC clock. > > Cc: Javier Martinez Canillas > Signed-off-by: Ben Gamari > Signed-off-by: Bartlomiej Zolnierkiewicz > --- > arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > This looks like a very-non-atomic way of handling a change. You added opp tables to exynos5420 before so at that time they will be applied to Odroid XU3 family which uses different CPU order. After that you are fixing the tables to proper CPU order. Direct bisectability probably won't be an issue because all of DTS would go to separate branch... but the logic behind confuses. I think this should be squashed into 3/8. Best regards, Krzysztof > diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi > index b7f60c8..9a5131d 100644 > --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi > +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi > @@ -20,8 +20,10 @@ > device_type = "cpu"; > compatible = "arm,cortex-a7"; > reg = <0x100>; > + clocks = <&clock CLK_KFC_CLK>; > clock-frequency = <1000000000>; > cci-control-port = <&cci_control0>; > + operating-points-v2 = <&cpu1_opp_table>; > }; > > &cpu1 { > @@ -30,6 +32,7 @@ > reg = <0x101>; > clock-frequency = <1000000000>; > cci-control-port = <&cci_control0>; > + operating-points-v2 = <&cpu1_opp_table>; > }; > > &cpu2 { > @@ -38,6 +41,7 @@ > reg = <0x102>; > clock-frequency = <1000000000>; > cci-control-port = <&cci_control0>; > + operating-points-v2 = <&cpu1_opp_table>; > }; > > &cpu3 { > @@ -46,14 +50,17 @@ > reg = <0x103>; > clock-frequency = <1000000000>; > cci-control-port = <&cci_control0>; > + operating-points-v2 = <&cpu1_opp_table>; > }; > > &cpu4 { > device_type = "cpu"; > compatible = "arm,cortex-a15"; > reg = <0x0>; > + clocks = <&clock CLK_ARM_CLK>; > clock-frequency = <1800000000>; > cci-control-port = <&cci_control1>; > + operating-points-v2 = <&cpu0_opp_table>; > }; > > &cpu5 { > @@ -62,6 +69,7 @@ > reg = <0x1>; > clock-frequency = <1800000000>; > cci-control-port = <&cci_control1>; > + operating-points-v2 = <&cpu0_opp_table>; > }; > > &cpu6 { > @@ -70,6 +78,7 @@ > reg = <0x2>; > clock-frequency = <1800000000>; > cci-control-port = <&cci_control1>; > + operating-points-v2 = <&cpu0_opp_table>; > }; > > &cpu7 { > @@ -78,4 +87,5 @@ > reg = <0x3>; > clock-frequency = <1800000000>; > cci-control-port = <&cci_control1>; > + operating-points-v2 = <&cpu0_opp_table>; > }; >