From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754213AbbLIXXk (ORCPT ); Wed, 9 Dec 2015 18:23:40 -0500 Received: from mga09.intel.com ([134.134.136.24]:6799 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751600AbbLIXXj (ORCPT ); Wed, 9 Dec 2015 18:23:39 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,405,1444719600"; d="scan'208";a="10571156" Subject: Re: [PATCH 1/1] perf/x86/intel: Add perf core PMU support for Intel Knights Landing To: Peter Zijlstra References: <20151208083757.GD6356@twins.programming.kicks-ass.net> Cc: linux-kernel@vger.kernel.org, mingo@redhat.com, Harish Chegondi , Andi Kleen , Kan Liang , Lukasz Anaczkowski From: Harish Chegondi Message-ID: <5668B7B4.9070102@intel.com> Date: Wed, 9 Dec 2015 15:22:29 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20151208083757.GD6356@twins.programming.kicks-ass.net> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/08/2015 12:37 AM, Peter Zijlstra wrote: > On Mon, Dec 07, 2015 at 02:28:18PM -0800, Harish Chegondi wrote: >> Knights Landing core is based on Silvermont core with several differences. >> Like Silvermont, Knights Landing has 8 pairs of LBR MSRs. However, the >> LBR MSRs addresses match those of the Xeon cores' first 8 pairs of LBR MSRs > >> +/* Knights Landing */ >> +void intel_pmu_lbr_init_knl(void) >> +{ >> + x86_pmu.lbr_nr = 8; >> + x86_pmu.lbr_tos = MSR_LBR_TOS; >> + x86_pmu.lbr_from = MSR_LBR_NHM_FROM; >> + x86_pmu.lbr_to = MSR_LBR_NHM_TO; >> + >> + x86_pmu.lbr_sel_mask = LBR_SEL_MASK; >> + x86_pmu.lbr_sel_map = snb_lbr_sel_map; > Also, unlike Silvermont, this thing seems to have hardware LBR filters. > So would it not be more accurate to say the KNL has a big core LBR > instead? (Note that this LBR setup isn't specific to Xeon's, all of the > Core chips have this, including the client parts). We cannot say that KNL has a big core LBR. This is because architectural MSR IA32_PERF_CAPABILITIES[5:0] which indicates the format of the address that is stored in the LBR stack is different for KNL (IA32_PERF_CAPABILITIES[5:0] = 0x1) and big core (for example, Haswell IA32_PERF_CAPABILITIES[5:0]=0x4). Haswell LBR stack has TSX info which KNL LBR stack doesn't have. Thanks for the review! > >> + pr_cont("8-deep LBR, "); >> +} > . >