From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754164AbbLJBUY (ORCPT ); Wed, 9 Dec 2015 20:20:24 -0500 Received: from mailout2.w1.samsung.com ([210.118.77.12]:24593 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751582AbbLJBUU (ORCPT ); Wed, 9 Dec 2015 20:20:20 -0500 MIME-version: 1.0 Content-type: text/plain; charset=utf-8 X-AuditID: cbfec7f4-f79026d00000418a-99-5668d351f7a7 Content-transfer-encoding: 8BIT Subject: Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250 To: Chanwoo Choi , myungjoo.ham@samsung.com, kgene@kernel.org References: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> <1449634091-1842-4-git-send-email-cw00.choi@samsung.com> <5668CADE.8090706@samsung.com> <5668D0B6.1030902@samsung.com> Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org From: Krzysztof Kozlowski Message-id: <5668D34B.1010602@samsung.com> Date: Thu, 10 Dec 2015 10:20:11 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-reply-to: <5668D0B6.1030902@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDIsWRmVeSWpSXmKPExsVy+t/xq7qBlzPCDB5+k7O4/uU5q8X8I+dY LfrfLGS1OPdqJaPF6xeGFv2PXzNbnG16w25xedccNovPvUcYLWac38dksW7jLXaL25d5LZZe v8hkcbtxBZvFhOlrWSxa9x5ht2hb/YHVQdBjzbw1jB4tzT1sHpf7epk8ds66y+6xcvkXNo9N qzrZPP4dY/fo27KK0ePzJrkAzigum5TUnMyy1CJ9uwSujG1bpzMWPBOtaH4/kaWBcZVgFyMn h4SAicSNpm52CFtM4sK99WxdjFwcQgJLGSX2rJ/GCJLgFRCU+DH5HksXIwcHs4C8xJFL2RCm usSUKbkQ5U8ZJfb/OA82R1jAXeLYr+NMILaIQJjE7Bk/mCGK9jNKTP0xD8xhFrjLJHHx/RM2 kCo2AWOJzcuXsEEs05J4u/8N2GIWAVWJ/w+mMYNsExWIkFi0IxMkzCmgLbF/xQqWCYwCs5Cc NwvhvFkI5y1gZF7FKJpamlxQnJSea6hXnJhbXJqXrpecn7uJERJnX3YwLj5mdYhRgINRiYf3 gkt6mBBrYllxZe4hRgkOZiUR3mkXMsKEeFMSK6tSi/Lji0pzUosPMUpzsCiJ887d9T5ESCA9 sSQ1OzW1ILUIJsvEwSnVwFi+9ua6zwcYs7SeLFvyRv/rMee9Kx8GqTMf5Z+x68ELnmRDppbj q2X+H3g5uVl5iveeiOjl2ycvmhhS+nfOJo4pZiVWa5c/fPmkd5oz2/Iikdn+OwK/rH7nKvH+ yRyT6AXbtCPmVpa9XXLMOlBvfzT7IsfSJOdLOsWCnfaRFfu5xXw/zJS3zN6pxFKckWioxVxU nAgAIsNC1q8CAAA= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10.12.2015 10:09, Chanwoo Choi wrote: > On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote: >> On 09.12.2015 13:07, Chanwoo Choi wrote: >>> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC. >>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard >>> SDRAM devices. The bus includes the OPP tables and the source clock for DMC >>> block. >>> >>> Following list specifies the detailed relation between the clock and DMC block: >>> - The source clock of DMC block : div_dmc >>> >>> Signed-off-by: Chanwoo Choi >>> --- >>> arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++ >>> 1 file changed, 34 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi >>> index 2f30d632f1cc..7214c5e42150 100644 >>> --- a/arch/arm/boot/dts/exynos3250.dtsi >>> +++ b/arch/arm/boot/dts/exynos3250.dtsi >>> @@ -687,6 +687,40 @@ >>> clock-names = "ppmu"; >>> status = "disabled"; >>> }; >>> + >>> + bus_dmc: bus_dmc { >>> + compatible = "samsung,exynos-bus"; >>> + clocks = <&cmu_dmc CLK_DIV_DMC>; >>> + clock-names = "bus"; >>> + operating-points-v2 = <&bus_dmc_opp_table>; >>> + status = "disabled"; >>> + }; >>> + >>> + bus_dmc_opp_table: opp_table1 { >> >> This is the firsy opp_table, right? So: >> s/opp_table1/opp_table0/ > > Right. It is first opp_table in exynos3250.dtsi. > But, I'm considering the OPP table of CPU freqeuncy as opp_table0. > So, I have the plan that support the operation-points-v2 for Exynos3250 CPU. Ok > >> >>> + compatible = "operating-points-v2"; >>> + opp-shared; >>> + >>> + opp00 { >>> + opp-hz = /bits/ 64 <50000000>; >>> + opp-microvolt = <800000>; >>> + }; >>> + opp01 { >>> + opp-hz = /bits/ 64 <100000000>; >>> + opp-microvolt = <800000>; >>> + }; >>> + opp02 { >>> + opp-hz = /bits/ 64 <134000000>; >>> + opp-microvolt = <800000>; >> >> Why 134, not 133 MHz? > > When I used the 133000000, the source clock is changed to 100Mhz instead of 133MHz. > I add following test result on exynos3250-rinato board. > > Case1. > When I use the 134 MHz, the source clock is changed to 133MHz > : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (134000000) (real: 133333334) > > Case2. > When I use the 133 MHz, the source clock is changed to 100MHz > : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (133000000) (real: 100000000) Now I remember that issue. You could use here directly 133333334 but that also would look a little bit weird... so 134 is ok for me. Could just add a comment that desired frequency is actually "133 MHz"? Best regards, Krzysztof