From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753887AbbLJCE7 (ORCPT ); Wed, 9 Dec 2015 21:04:59 -0500 Received: from mailout2.w1.samsung.com ([210.118.77.12]:25269 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751914AbbLJCE5 (ORCPT ); Wed, 9 Dec 2015 21:04:57 -0500 MIME-version: 1.0 Content-type: text/plain; charset=utf-8 X-AuditID: cbfec7f5-f79b16d000005389-a6-5668ddc5896c Content-transfer-encoding: 8BIT Subject: Re: [PATCH v2 03/19] ARM: dts: Add DMC bus node for Exynos3250 To: Chanwoo Choi , myungjoo.ham@samsung.com, kgene@kernel.org References: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> <1449634091-1842-4-git-send-email-cw00.choi@samsung.com> <5668CADE.8090706@samsung.com> <5668D0B6.1030902@samsung.com> <5668D34B.1010602@samsung.com> <5668DCDB.8020609@samsung.com> Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org From: Krzysztof Kozlowski Message-id: <5668DDBF.2070305@samsung.com> Date: Thu, 10 Dec 2015 11:04:47 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-reply-to: <5668DCDB.8020609@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprNIsWRmVeSWpSXmKPExsVy+t/xq7pH72aEGfxboG5x/ctzVov5R86x WvS/Wchqce7VSkaL1y8MLfofv2a2ONv0ht3i8q45bBafe48wWsw4v4/JYt3GW+wWty/zWiy9 fpHJ4nbjCjaLCdPXsli07j3CbtG2+gOrg6DHmnlrGD1amnvYPC739TJ57Jx1l91j5fIvbB6b VnWyefw7xu7Rt2UVo8fnTXIBnFFcNimpOZllqUX6dglcGadXP2EsmCtTsWD2I+YGxp1iXYyc HBICJhJt12+xQNhiEhfurWfrYuTiEBJYyihxf1czE0iCV0BQ4sfke0BFHBzMAvISRy5lQ5jq ElOm5EKUP2WUaJk9gxmkXFjAXeLYr+NgrSICYRKzZ/xghij6zyjx99ZTRhCHWeAuk8TF90/Y QKrYBIwlNi9fwgaxTEti2/tvjCA2i4CqxP1PIDUcHKICERKLdmSCmJwC2hKb2lknMArMQnLd LITrZiFct4CReRWjaGppckFxUnqukV5xYm5xaV66XnJ+7iZGSJR93cG49JjVIUYBDkYlHt4K p/QwIdbEsuLK3EOMEhzMSiK8XbcywoR4UxIrq1KL8uOLSnNSiw8xSnOwKInzztz1PkRIID2x JDU7NbUgtQgmy8TBKdXAyJ30QU+0uGTq0YhFzdO+iWxdJKs+9/K529vMOyf9k6lhDG1KfugZ zOS/8M02VvH6RE/rsP1a6sUKR97tl5S04U6OzNp6NfJ+pp37m8B90pO7OKt2rzRcZ3P9LbO7 pvfTW2sX5Rar758zWfxXWKeLtsnLjLQvTVPMDbeKP9/XYJH5c/WN0J1lSizFGYmGWsxFxYkA tvgd1K4CAAA= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10.12.2015 11:00, Chanwoo Choi wrote: > On 2015년 12월 10일 10:20, Krzysztof Kozlowski wrote: >> On 10.12.2015 10:09, Chanwoo Choi wrote: >>> On 2015년 12월 10일 09:44, Krzysztof Kozlowski wrote: >>>> On 09.12.2015 13:07, Chanwoo Choi wrote: >>>>> This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC. >>>>> The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard >>>>> SDRAM devices. The bus includes the OPP tables and the source clock for DMC >>>>> block. >>>>> >>>>> Following list specifies the detailed relation between the clock and DMC block: >>>>> - The source clock of DMC block : div_dmc >>>>> >>>>> Signed-off-by: Chanwoo Choi >>>>> --- >>>>> arch/arm/boot/dts/exynos3250.dtsi | 34 ++++++++++++++++++++++++++++++++++ >>>>> 1 file changed, 34 insertions(+) >>>>> >>>>> diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi >>>>> index 2f30d632f1cc..7214c5e42150 100644 >>>>> --- a/arch/arm/boot/dts/exynos3250.dtsi >>>>> +++ b/arch/arm/boot/dts/exynos3250.dtsi >>>>> @@ -687,6 +687,40 @@ >>>>> clock-names = "ppmu"; >>>>> status = "disabled"; >>>>> }; >>>>> + >>>>> + bus_dmc: bus_dmc { >>>>> + compatible = "samsung,exynos-bus"; >>>>> + clocks = <&cmu_dmc CLK_DIV_DMC>; >>>>> + clock-names = "bus"; >>>>> + operating-points-v2 = <&bus_dmc_opp_table>; >>>>> + status = "disabled"; >>>>> + }; >>>>> + >>>>> + bus_dmc_opp_table: opp_table1 { >>>> >>>> This is the firsy opp_table, right? So: >>>> s/opp_table1/opp_table0/ >>> >>> Right. It is first opp_table in exynos3250.dtsi. >>> But, I'm considering the OPP table of CPU freqeuncy as opp_table0. >>> So, I have the plan that support the operation-points-v2 for Exynos3250 CPU. >> >> Ok >> >>> >>>> >>>>> + compatible = "operating-points-v2"; >>>>> + opp-shared; >>>>> + >>>>> + opp00 { >>>>> + opp-hz = /bits/ 64 <50000000>; >>>>> + opp-microvolt = <800000>; >>>>> + }; >>>>> + opp01 { >>>>> + opp-hz = /bits/ 64 <100000000>; >>>>> + opp-microvolt = <800000>; >>>>> + }; >>>>> + opp02 { >>>>> + opp-hz = /bits/ 64 <134000000>; >>>>> + opp-microvolt = <800000>; >>>> >>>> Why 134, not 133 MHz? >>> >>> When I used the 133000000, the source clock is changed to 100Mhz instead of 133MHz. >>> I add following test result on exynos3250-rinato board. >>> >>> Case1. >>> When I use the 134 MHz, the source clock is changed to 133MHz >>> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (134000000) (real: 133333334) >>> >>> Case2. >>> When I use the 133 MHz, the source clock is changed to 100MHz >>> : exynos-bus soc:bus_dmc: old_freq(200000000) -> new_freq (133000000) (real: 100000000) >> >> Now I remember that issue. You could use here directly 133333334 but >> that also would look a little bit weird... so 134 is ok for me. Could >> just add a comment that desired frequency is actually "133 MHz"? > > Do you prefer among following example? > > Example1. > opp02 { > /* The desired frequency is 133MHz because > * clock change has the dependency on clock driver. > * When set rate as 134MHz, the clock driver would > * change the 133MHz actually instead of 134MHz. > */ > opp-hz = /bits/ 64 <134000000>; > opp-microvolt = <800000>; > }; > > Example2. > opp02 { > opp-hz = /bits/ 64 <133333334>; > opp-microvolt = <800000>; > }; I would prefer the second one (133333334) but I don't have strong feelings about it. Best regards, Krzysztof