From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752021AbbLJCJl (ORCPT ); Wed, 9 Dec 2015 21:09:41 -0500 Received: from mailout1.w1.samsung.com ([210.118.77.11]:24788 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750715AbbLJCJi (ORCPT ); Wed, 9 Dec 2015 21:09:38 -0500 X-AuditID: cbfec7f4-f79026d00000418a-d3-5668dedfb2a6 Subject: Re: [PATCH v2 12/19] ARM: dts: Add bus nodes using VDD_INT for Exynos3250 To: Chanwoo Choi , myungjoo.ham@samsung.com, kgene@kernel.org References: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> <1449634091-1842-13-git-send-email-cw00.choi@samsung.com> Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org From: Krzysztof Kozlowski Message-id: <5668DED7.3020403@samsung.com> Date: Thu, 10 Dec 2015 11:09:27 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-version: 1.0 In-reply-to: <1449634091-1842-13-git-send-email-cw00.choi@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDIsWRmVeSWpSXmKPExsVy+t/xy7r372WEGZzsU7C4/uU5q8X8I+dY LfrfLGS1OPdqJaPF6xeGFv2PXzNbnG16w25xedccNovPvUcYLWac38dksW7jLXaL25d5LZZe v8hkcbtxBZvFhOlrWSxa9x5ht2hb/YHVQdBjzbw1jB4tzT1sHpf7epk8ds66y+6xcvkXNo9N qzrZPP4dY/fo27KK0ePzJrkAzigum5TUnMyy1CJ9uwSujGev9jEW/JKrWPu5ibmB8bx4FyMn h4SAicTsPTMZIWwxiQv31rN1MXJxCAksZZS4/PIIK4TzlFFiZvdBVpAqYYEQiaXrvrCA2CIC YRKzZ/xgBrGFBBoYJd63poI0MAvcZZK4+P4JG0iCTcBYYvPyJWA2r4CWxJO9TWANLAKqEhsO 9LJ3MXJwiApESCzakQlRIijxY/I9FpAwp4CbxMKWGhCTWUBP4v5FLZAKZgF5ic1r3jJPYBSY haRhFkLVLCRVCxiZVzGKppYmFxQnpeca6hUn5haX5qXrJefnbmKExNmXHYyLj1kdYhTgYFTi 4b3gkh4mxJpYVlyZe4hRgoNZSYQ3/m5GmBBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHeubvehwgJ pCeWpGanphakFsFkmTg4pRoYfe6dyLKtjO3Se8jwOb5t+cFzB3WZvvBdcpWdWlbD9srzW4xt G9Ncnemuwhcasnq+r17266BQpNDBW8H+0/aYB4edv9FxPW3Tvz3HfPg+hkk4WOs+NLMOb5Fa q1ot7Hip07I1cRIjz/Kp7l5nvm4LFV93x3Uvs8HV/vyXGjkK6p9Vnf2nWikqsRRnJBpqMRcV JwIAwimV/68CAAA= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09.12.2015 13:08, Chanwoo Choi wrote: > This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. > Exynos3250 has following AXI buses to translate data between > DRAM and sub-blocks. > > Following list specifies the detailed relation between DRAM and sub-blocks: > - ACLK400 clock for MCUISP > - ACLK266 clock for ISP > - ACLK200 clock for FSYS > - ACLK160 clock for LCD0 > - ACLK100 clock for PERIL > - GDL clock for LEFTBUS > - GDR clock for RIGHTBUS > - SCLK_MFC clock for MFC > > Signed-off-by: Chanwoo Choi > --- > arch/arm/boot/dts/exynos3250.dtsi | 160 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 160 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi > index 7214c5e42150..46dee1951ec1 100644 > --- a/arch/arm/boot/dts/exynos3250.dtsi > +++ b/arch/arm/boot/dts/exynos3250.dtsi > @@ -721,6 +721,166 @@ > opp-microvolt = <875000>; > }; > }; > + > + bus_leftbus: bus_leftbus { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_GDL>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_leftbus_opp_table>; > + status = "disabled"; > + }; > + > + bus_rightbus: bus_rightbus { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_GDR>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_leftbus_opp_table>; > + status = "disabled"; > + }; > + > + bus_lcd0: bus_lcd0 { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_ACLK_160>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_leftbus_opp_table>; > + status = "disabled"; > + }; > + > + bus_fsys: bus_fsys { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_ACLK_200>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_leftbus_opp_table>; > + status = "disabled"; > + }; > + > + bus_mcuisp: bus_mcuisp { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_mcuisp_opp_table>; > + status = "disabled"; > + }; > + > + bus_isp: bus_isp { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_ACLK_266>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_isp_opp_table>; > + status = "disabled"; > + }; > + > + bus_peril: bus_peril { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_DIV_ACLK_100>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_peril_opp_table>; > + status = "disabled"; > + }; > + > + bus_mfc: bus_mfc { > + compatible = "samsung,exynos-bus"; > + clocks = <&cmu CLK_SCLK_MFC>; > + clock-names = "bus"; > + operating-points-v2 = <&bus_leftbus_opp_table>; > + status = "disabled"; > + }; > + > + bus_leftbus_opp_table: opp_table2 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp00 { > + opp-hz = /bits/ 64 <50000000>; > + opp-microvolt = <900000>; > + }; > + opp01 { > + opp-hz = /bits/ 64 <80000000>; > + opp-microvolt = <900000>; > + }; > + opp02 { > + opp-hz = /bits/ 64 <100000000>; > + opp-microvolt = <1000000>; > + }; > + opp03 { > + opp-hz = /bits/ 64 <134000000>; > + opp-microvolt = <1000000>; > + }; > + opp04 { > + opp-hz = /bits/ 64 <200000000>; > + opp-microvolt = <1000000>; > + }; > + }; > + > + bus_mcuisp_opp_table: opp_table3 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp00 { > + opp-hz = /bits/ 64 <50000000>; > + opp-microvolt = <900000>; The voltages for all these INT-block tables have exactly the same value which of course makes sense because this is the same regulator. However the opp-microvolt property is an optional property. Do you have to provide it in each OPP? Best regards, Krzysztof