From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753985AbbLJEVY (ORCPT ); Wed, 9 Dec 2015 23:21:24 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:46145 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752586AbbLJEVV (ORCPT ); Wed, 9 Dec 2015 23:21:21 -0500 MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 X-AuditID: cbfee68f-f793a6d000001364-6b-5668fdbf326d Content-transfer-encoding: 8BIT Message-id: <5668FDBF.1010304@samsung.com> Date: Thu, 10 Dec 2015 13:21:19 +0900 From: Chanwoo Choi User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 To: Krzysztof Kozlowski , myungjoo.ham@samsung.com, kgene@kernel.org Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 References: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> <1449634091-1842-14-git-send-email-cw00.choi@samsung.com> <5668EEC0.80403@samsung.com> In-reply-to: <5668EEC0.80403@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPIsWRmVeSWpSXmKPExsWyRsSkUHf/34wwg3c3LC3mHznHatH/ZiGr xblXKxktXr8wtOh//JrZ4mzTG3aLy7vmsFl87j3CaDHj/D4mi3Ubb7Fb3L7Ma7H0+kUmi9uN K9gsJkxfy2LRuvcIu0Xb6g+sDgIea+atYfRoae5h87jc18vksXPWXXaPlcu/sHlsWtXJ5vHv GLtH35ZVjB6fN8kFcEZx2aSk5mSWpRbp2yVwZUx9vJ6lYJpgxc8fnxgbGI/zdjFyckgImEhs WDCDEcIWk7hwbz1bFyMXh5DACkaJjR9uMXUxcoAV/bhsBRGfxShxevYKVpAGXgFBiR+T77GA 1DALyEscuZQNEmYWUJeYNG8RM4gtJPCAUeLFjXyIci2JjU8OsoHYLAKqEke2tYDVsAHF97+4 wQYyRlQgQqL7RCVIWEQgXmLTi6tg5zAL3GWSuPj+CVivsECIxM25Jxgh7pnPKNE4dRsLSIJT QFPiRdM5sA4JgR0cEgd/r2KH2CYg8W3yIRaIZ2QlNh1ghnhYUuLgihssExjFZiF5ZxbCO7OQ vLOAkXkVo2hqQXJBcVJ6kbFecWJucWleul5yfu4mRmC8n/73rH8H490D1ocYBTgYlXh4L7ik hwmxJpYVV+YeYjQFOmIis5Rocj4wqeSVxBsamxlZmJqYGhuZW5opifMulPoZLCSQnliSmp2a WpBaFF9UmpNafIiRiYNTqoExwGSL1JOSCXWnz3NYRqzgW/4gamHkml/iL75oP7VtviX12TGX KebX3G1c30OCL7LUec3fcSsnoHrjTctbG7sSIy8sdXrAqLM1iin0/4JfNya+CrPn2PVs3vYb /Jyqy8+t+enn61h+pGjj42/mCww5tp1J5TF5n9lY5GH0Yo/ka8WgvZ77C+8KKrEUZyQaajEX FScCAOpKpC7yAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrDKsWRmVeSWpSXmKPExsVy+t9jQd39fzPCDO7vMbaYf+Qcq0X/m4Ws FuderWS0eP3C0KL/8Wtmi7NNb9gtLu+aw2bxufcIo8WM8/uYLNZtvMVucfsyr8XS6xeZLG43 rmCzmDB9LYtF694j7BZtqz+wOgh4rJm3htGjpbmHzeNyXy+Tx85Zd9k9Vi7/wuaxaVUnm8e/ Y+wefVtWMXp83iQXwBnVwGiTkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pmYKhraGlhrqSQl5ib aqvk4hOg65aZA/SFkkJZYk4pUCggsbhYSd8O04TQEDddC5jGCF3fkCC4HiMDNJCwhjFj6uP1 LAXTBCt+/vjE2MB4nLeLkYNDQsBE4sdlqy5GTiBTTOLCvfVsXYxcHEICsxglTs9ewQqS4BUQ lPgx+R4LSD2zgLzEkUvZIGFmAXWJSfMWMYPYQgIPGCVe3MiHKNeS2PjkIBuIzSKgKnFkWwtY DRtQfP+LG2wgY0QFIiS6T1SChEUE4iU2vbgKtpZZ4C6TxMX3T8B6hQVCJG7OPcEIcc98RonG qdtYQBKcApoSL5rOsU1gBLoS4bxZCOfNQnLeAkbmVYwSqQXJBcVJ6bmGeanlesWJucWleel6 yfm5mxjBKeWZ1A7Gg7vcDzEKcDAq8fBecEkPE2JNLCuuzD3EKMHBrCTCe/RnRpgQb0piZVVq UX58UWlOavEhRlOgBycyS4km5wPTXV5JvKGxiZmRpZG5oYWRsbmSOG/tpcgwIYH0xJLU7NTU gtQimD4mDk6pBsbD7kpf1zpaHC6/FzNVTsWwrF22aArrkco/OTwbV82a2b7h085DbALl5zb6 N2bX283vzt1s0fCG+925h1OPWqSf37hDf8Zyq72Tz/xR+nxcMaqx1tO2zt7m2tWXkgJVyed3 Hl4QvaHaMfbE8v0VVQXLON6YKhl+/PhoWl5Pf/wM34CSE54rHGyUWIozEg21mIuKEwG5b/Dy PwMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2015년 12월 10일 12:17, Krzysztof Kozlowski wrote: > On 09.12.2015 13:08, Chanwoo Choi wrote: >> This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC. > > s/noes/nodes/ OK. > >> Exynos4x12 has the following AXI buses to translate data >> between DRAM and DMC/ACP/C2C. >> >> Signed-off-by: Chanwoo Choi >> --- >> arch/arm/boot/dts/exynos4x12.dtsi | 72 +++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 72 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi >> index b77dac61ffb5..3bcf0939755e 100644 >> --- a/arch/arm/boot/dts/exynos4x12.dtsi >> +++ b/arch/arm/boot/dts/exynos4x12.dtsi >> @@ -282,6 +282,78 @@ >> clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; >> #iommu-cells = <0>; >> }; >> + >> + bus_dmc: bus_dmc { >> + compatible = "samsung,exynos-bus"; >> + clocks = <&clock CLK_DIV_DMC>; >> + clock-names = "bus"; >> + operating-points-v2 = <&bus_dmc_opp_table>; >> + status = "disabled"; >> + }; >> + >> + bus_acp: bus_acp { >> + compatible = "samsung,exynos-bus"; >> + clocks = <&clock CLK_DIV_ACP>; >> + clock-names = "bus"; >> + operating-points-v2 = <&bus_acp_opp_table>; >> + status = "disabled"; >> + }; >> + >> + bus_c2c: bus_c2c { >> + compatible = "samsung,exynos-bus"; >> + clocks = <&clock CLK_DIV_C2C>; >> + clock-names = "bus"; >> + operating-points-v2 = <&bus_dmc_opp_table>; >> + status = "disabled"; >> + }; >> + >> + bus_dmc_opp_table: opp_table1 { >> + compatible = "operating-points-v2"; >> + opp-shared; >> + >> + opp00 { >> + opp-hz = /bits/ 64 <100000000>; >> + opp-microvolt = <900000>; >> + }; >> + opp01 { >> + opp-hz = /bits/ 64 <134000000>; >> + opp-microvolt = <900000>; >> + }; >> + opp02 { >> + opp-hz = /bits/ 64 <160000000>; >> + opp-microvolt = <900000>; >> + }; >> + opp03 { >> + opp-hz = /bits/ 64 <200000000>; >> + opp-microvolt = <950000>; > > The exyno4_bus.c (from mainline) uses 267 MHz here. Why choosing 200 MHz? There is no special reason. I'll change it (200MHz -> 267MHz). Best Regards, Chanwoo Choi