From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753004AbbLJGca (ORCPT ); Thu, 10 Dec 2015 01:32:30 -0500 Received: from mailout3.w1.samsung.com ([210.118.77.13]:26771 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751628AbbLJGc2 (ORCPT ); Thu, 10 Dec 2015 01:32:28 -0500 MIME-version: 1.0 Content-type: text/plain; charset=utf-8 X-AuditID: cbfec7f5-f79b16d000005389-66-56691c79bd0c Content-transfer-encoding: 8BIT Subject: Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12 To: Chanwoo Choi , myungjoo.ham@samsung.com, kgene@kernel.org References: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> <1449634091-1842-15-git-send-email-cw00.choi@samsung.com> <56691458.9000000@samsung.com> <566916E5.5060704@samsung.com> Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org From: Krzysztof Kozlowski Message-id: <56691C70.6080208@samsung.com> Date: Thu, 10 Dec 2015 15:32:16 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 In-reply-to: <566916E5.5060704@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDIsWRmVeSWpSXmKPExsVy+t/xy7qVMplhBh9vsFtc//Kc1WL+kXOs Fv1vFrJanHu1ktHi9QtDi/7Hr5ktzja9Ybe4vGsOm8Xn3iOMFjPO72OyWLfxFrvF7cu8Fkuv X2SyuN24gs1iwvS1LBate4+wW7St/sDqIOixZt4aRo+W5h42j8t9vUweO2fdZfdYufwLm8em VZ1sHv+OsXv0bVnF6PF5k1wAZxSXTUpqTmZZapG+XQJXxuZDE9gK1olW7Fq3namBcZFgFyMn h4SAicTLmWvYIWwxiQv31rN1MXJxCAksZZTY9WMWWIJXQFDix+R7LF2MHBzMAvISRy5lQ5jq ElOm5EKU/2KU2PN6LitIubBAiMSmeWvAbBGBMInZM34wQxQdYJQ40D2JEcRhFrjLJHHx/RM2 kCo2AWOJzcuXsEEs05LYPqcTzGYRUJW49QRkEgeHqECExKIdmSBhTgFtiRP/djNPYBSYheS8 WQjnzUI4bwEj8ypG0dTS5ILipPRcI73ixNzi0rx0veT83E2MkDj7uoNx6TGrQ4wCHIxKPLwV TulhQqyJZcWVuYcYJTiYlUR4j/7MCBPiTUmsrEotyo8vKs1JLT7EKM3BoiTOO3PX+xAhgfTE ktTs1NSC1CKYLBMHp1QD49agLxktPGuvsoa6bAvZ9Dgu0f9snvyV+BNTJpicUJDxLfj0TGnP 83j+QtGKmb2u0d6Ht6ml/vw4+92urYeWi0Xs4HH6XfP23ONU+dZlx5rO7lacsvbpqtLU6w3d /a3Fy+d0F0TvTJbwbCqS4FqVFOnEU9gW7VT18InyFveL33n0swXMptUEKLEUZyQaajEXFScC APTzDsavAgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10.12.2015 15:08, Chanwoo Choi wrote: > On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote: >> On 09.12.2015 13:08, Chanwoo Choi wrote: >>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC. >>> Exynos4x12 has the following AXI buses to translate data between >>> DRAM and sub-blocks. >>> >>> Following list specifies the detailed relation between DRAM and sub-blocks: >>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK) >>> - ACLK160 clock for CAM/TV/LCD >>> : The minimum clock of ACLK160 should be over 160MHz. >>> When drop the clock under 160MHz, show the broken image. >>> - ACLK133 clock for FSYS >>> - GDL clock for LEFTBUS >>> - GDR clock for RIGHTBUS >>> - SCLK_MFC clock for MFC >>> >>> Signed-off-by: Chanwoo Choi >>> --- >>> arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 112 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi >>> index 3bcf0939755e..8bc4aee156b5 100644 >>> --- a/arch/arm/boot/dts/exynos4x12.dtsi >>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi >>> @@ -354,6 +354,118 @@ >>> opp-microvolt = <950000>; >>> }; >>> }; >>> + >>> + bus_leftbus: bus_leftbus { >>> + compatible = "samsung,exynos-bus"; >>> + clocks = <&clock CLK_DIV_GDL>; >>> + clock-names = "bus"; >>> + operating-points-v2 = <&bus_leftbus_opp_table>; >>> + status = "disabled"; >>> + }; >>> + >>> + bus_rightbus: bus_rightbus { >>> + compatible = "samsung,exynos-bus"; >>> + clocks = <&clock CLK_DIV_GDR>; >>> + clock-names = "bus"; >>> + operating-points-v2 = <&bus_leftbus_opp_table>; >>> + status = "disabled"; >>> + }; >> >> These two nodes are symmetrical. The MFC below and other buses in other >> DTS share opps. How about changing the binding so multiple clocks could >> be specified at once ("bus0", "bus1")? I think there is no need for a >> bus device for each clock. > > The your commented method is possible. > > But, I focus on implementing the generic bus frequency driver. > > If specific bus device-tree node includes the one more clocks, > when adding the new Exynos SoC, the exynos-bus.c should be added > for new Exynos SoC. Because, each Exynos SoC has the different > set of bus device. > > If we use my approach, we don't need to modify the exynos-bus.c > driver to support for the bus frequency of new Exynos SoC. This won't change. The driver will just support from 1 to N clocks for given bus device and set the same OPP to all of them. This will only limit the number of duplicated entries. This won't affect the generic approach of driver itself. Best regards, Krzysztof