From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753077AbbLJGoN (ORCPT ); Thu, 10 Dec 2015 01:44:13 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:51782 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751884AbbLJGoJ convert rfc822-to-8bit (ORCPT ); Thu, 10 Dec 2015 01:44:09 -0500 X-AuditID: cbfee68d-f79646d000001355-ca-56691f296224 MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 8BIT Message-id: <56691F29.1020808@samsung.com> Date: Thu, 10 Dec 2015 15:43:53 +0900 From: Chanwoo Choi User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 To: Krzysztof Kozlowski , myungjoo.ham@samsung.com, kgene@kernel.org Cc: kyungmin.park@samsung.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, linux.amoon@gmail.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 14/19] ARM: dts: Add bus nodes using VDD_INT for Exynos4x12 References: <1449634091-1842-1-git-send-email-cw00.choi@samsung.com> <1449634091-1842-15-git-send-email-cw00.choi@samsung.com> <56691458.9000000@samsung.com> <566916E5.5060704@samsung.com> <56691C70.6080208@samsung.com> In-reply-to: <56691C70.6080208@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOIsWRmVeSWpSXmKPExsWyRsSkUFdLPjPMYOkyZov5R86xWvS/Wchq ce7VSkaL1y8MLfofv2a2ONv0ht3i8q45bBafe48wWsw4v4/JYt3GW+wWty/zWiy9fpHJ4nbj CjaLCdPXsli07j3CbtG2+gOrg4DHmnlrGD1amnvYPC739TJ57Jx1l91j5fIvbB6bVnWyefw7 xu7Rt2UVo8fnTXIBnFFcNimpOZllqUX6dglcGTtWXGEpOKtYcXzyFJYGxpvSXYycHBICJhJ7 929ig7DFJC7cWw9kc3EICaxglDi4fScrTFHz8kfsEImljBJzph8F6+AVEJT4MfkeSxcjBwez gLrElCm5EKaIxPJl6iAVzALaEssWvmaGaH3AKPH+5HJ2iFYtiRkPdjKD2CwCqhLb+n6A7WID iu9/cYMNZI6oQIRE94lKkLCIQLzEphdXwW5jFrjLJHHx/ROwE4QFQiQ2zVvDCrHgIaPE4Vdv WEASnECbpxzrBUtICGzhkDjx4jULxDYBiW+TD4EdLSEgK7HpADPEk5ISB1fcYJnAKD4LyWuz EF6bhfDaLCSvLWBkWcUomlqQXFCclF5kqFecmFtcmpeul5yfu4kRmB5O/3vWu4Px9gHrQ4wC HIxKPLwvpDPDhFgTy4orcw8xmgLdM5FZSjQ5H5iE8kriDY3NjCxMTUyNjcwtzZTEeRWlfgYL CaQnlqRmp6YWpBbFF5XmpBYfYmTi4JRqYPQKDWqf8bvKVvSjh9JtYyXHiyJuj59XXOrgE3R0 m9J7OHjDsT/8VYELPWw2sPx9x7o1Ol87btO8Sv3A3weZ83WPupwRfFLw8cTM4uDJB273uzZe 2vGZkd/R4Nfqyj1K7BNTtV+IP2L9dWGqnEVBmqOx4Em7VxvdP5u5/VIy+D7R/az0sdenfJRY ijMSDbWYi4oTAQyuWQQKAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrDKsWRmVeSWpSXmKPExsVy+t9jAV1N+cwwg2lfDC3mHznHatH/ZiGr xblXKxktXr8wtOh//JrZ4mzTG3aLy7vmsFl87j3CaDHj/D4mi3Ubb7Fb3L7Ma7H0+kUmi9uN K9gsJkxfy2LRuvcIu0Xb6g+sDgIea+atYfRoae5h87jc18vksXPWXXaPlcu/sHlsWtXJ5vHv GLtH35ZVjB6fN8kFcEY1MNpkpCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam 2iq5+AToumXmAH2hpFCWmFMKFApILC5W0rfDNCE0xE3XAqYxQtc3JAiux8gADSSsYcx42P+Z tWCiYkXL2hMsDYxzpbsYOTkkBEwkmpc/YoewxSQu3FvP1sXIxSEksJRRYs70o2wgCV4BQYkf k++xdDFycDALyEscuZQNYapLTJmSC1H+gFHi/cnl7BDlWhIzHuxkBrFZBFQltvX9YAWx2YDi +1/cYAPpFRWIkOg+UQkSFhGIl9j04irYWmaBu0wSF98/AVsrLBAisWneGlaIBQ8ZJQ6/esMC kuAU0JaYcqyXdQKjwCwk581COG8WwnkLGJlXMUqkFiQXFCel5xrmpZbrFSfmFpfmpesl5+du YgSnlGdSOxgP7nI/xCjAwajEw/tCOjNMiDWxrLgy9xCjBAezkgjv0Z8ZYUK8KYmVValF+fFF pTmpxYcYTYH+m8gsJZqcD0x3eSXxhsYmZkaWRuaGFkbG5krivLWXIsOEBNITS1KzU1MLUotg +pg4OKUaGOV+/uBvWtH4/9F5rocLEqc8V57292/y5R2JWbdNPt2USHk5zy+3dYKI8C2uqrjo o1m5LMudW/at8Fab8aLo9pEr65JCldd61Zq/LlnXox3CarzWecXaF2f2SOS8Lkq8ddZ6Tskf R1aBHXy93ir6G/QlI0OvhszoUT0x/xWv8r3V5+b+/CYddEmJpTgj0VCLuag4EQA4pIKxPwMA AA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2015년 12월 10일 15:32, Krzysztof Kozlowski wrote: > On 10.12.2015 15:08, Chanwoo Choi wrote: >> On 2015년 12월 10일 14:57, Krzysztof Kozlowski wrote: >>> On 09.12.2015 13:08, Chanwoo Choi wrote: >>>> This patch adds the bus noes using VDD_INT for Exynos4x12 SoC. >>>> Exynos4x12 has the following AXI buses to translate data between >>>> DRAM and sub-blocks. >>>> >>>> Following list specifies the detailed relation between DRAM and sub-blocks: >>>> - ACLK100 clock for PERIL/PERIR/MFC(PCLK) >>>> - ACLK160 clock for CAM/TV/LCD >>>> : The minimum clock of ACLK160 should be over 160MHz. >>>> When drop the clock under 160MHz, show the broken image. >>>> - ACLK133 clock for FSYS >>>> - GDL clock for LEFTBUS >>>> - GDR clock for RIGHTBUS >>>> - SCLK_MFC clock for MFC >>>> >>>> Signed-off-by: Chanwoo Choi >>>> --- >>>> arch/arm/boot/dts/exynos4x12.dtsi | 112 ++++++++++++++++++++++++++++++++++++++ >>>> 1 file changed, 112 insertions(+) >>>> >>>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi >>>> index 3bcf0939755e..8bc4aee156b5 100644 >>>> --- a/arch/arm/boot/dts/exynos4x12.dtsi >>>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi >>>> @@ -354,6 +354,118 @@ >>>> opp-microvolt = <950000>; >>>> }; >>>> }; >>>> + >>>> + bus_leftbus: bus_leftbus { >>>> + compatible = "samsung,exynos-bus"; >>>> + clocks = <&clock CLK_DIV_GDL>; >>>> + clock-names = "bus"; >>>> + operating-points-v2 = <&bus_leftbus_opp_table>; >>>> + status = "disabled"; >>>> + }; >>>> + >>>> + bus_rightbus: bus_rightbus { >>>> + compatible = "samsung,exynos-bus"; >>>> + clocks = <&clock CLK_DIV_GDR>; >>>> + clock-names = "bus"; >>>> + operating-points-v2 = <&bus_leftbus_opp_table>; >>>> + status = "disabled"; >>>> + }; >>> >>> These two nodes are symmetrical. The MFC below and other buses in other >>> DTS share opps. How about changing the binding so multiple clocks could >>> be specified at once ("bus0", "bus1")? I think there is no need for a >>> bus device for each clock. >> >> The your commented method is possible. >> >> But, I focus on implementing the generic bus frequency driver. >> >> If specific bus device-tree node includes the one more clocks, >> when adding the new Exynos SoC, the exynos-bus.c should be added >> for new Exynos SoC. Because, each Exynos SoC has the different >> set of bus device. >> >> If we use my approach, we don't need to modify the exynos-bus.c >> driver to support for the bus frequency of new Exynos SoC. > > This won't change. The driver will just support from 1 to N clocks for > given bus device and set the same OPP to all of them. This will only > limit the number of duplicated entries. This won't affect the generic > approach of driver itself. You're right aspect of only implementation of device driver. But, If we use your commented approach, we can show the information of only parent device through sysfs. We cannot see the information of passive device. The some information includes the current frequency and correlation of parent device. (But, current patchset don' include the topology information between parent device and passive device. I'll do it on later patches). For example, We can see the following bus device through /sys/class/devfreq. drwxr-xr-x 2 root root 0 Dec 31 17:00 . drwxr-xr-x 44 root root 0 Dec 31 17:00 .. lrwxrwxrwx 1 root root 0 Dec 31 17:00 bus_display -> ../../devices/platform/bus_display/devfreq/bus_display lrwxrwxrwx 1 root root 0 Dec 31 17:00 bus_fsys -> ../../devices/platform/bus_fsys/devfreq/bus_fsys lrwxrwxrwx 1 root root 0 Dec 31 17:00 bus_leftbus -> ../../devices/platform/bus_leftbus/devfreq/bus_leftbus lrwxrwxrwx 1 root root 0 Dec 31 17:00 bus_peri -> ../../devices/platform/bus_peri/devfreq/bus_peri We don't see the following bus device because of following bus device has the same frequency table with bus_leftbus device. lrwxrwxrwx 1 root root 0 Dec 31 17:00 bus_mfc -> ../../devices/platform/bus_mfc/devfreq/bus_mfc lrwxrwxrwx 1 root root 0 Dec 31 17:00 bus_rightbus -> ../../devices/platform/bus_rightbus/devfreq/bus_rightbus Best Regards, Chanwoo Choi