From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2221C77B7E for ; Thu, 1 Jun 2023 18:53:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231607AbjFASxE (ORCPT ); Thu, 1 Jun 2023 14:53:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229899AbjFASxC (ORCPT ); Thu, 1 Jun 2023 14:53:02 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CEE2137; Thu, 1 Jun 2023 11:53:01 -0700 (PDT) Received: from arisu.localnet (unknown [23.233.251.139]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by madras.collabora.co.uk (Postfix) with ESMTPSA id 621166606ECA; Thu, 1 Jun 2023 19:52:58 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685645579; bh=HA9WLCD2ceWYBo2r9YOQjN+RA/kPiPSlzAQ3oEd40Ng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Pha/7fjJpKB9OGSkoq37gQXG8fTg0POKJKClZoPz6/0RvQPywX/k9YoOC1WxRQ2uM jxn1n8rbEfdEkLFpBxbueb+GArIjeL+pork23RNdJtHJzfM8FGpEATYAi+lORycX8b nSqnE8RIyYATLyDAH8xCXBzmxJi/9P3sL6kuodZu4zD0gsBHpZUPcbcdhJwDfG3WnV D4Mu9HHJZxIkU8Aya0Yyf1X3wVbSBhWGxsDp14Bj2OMQMHLBToXqedhZN58Appkh1w 7KwYMdgfpVVShy200svEQTO1RbeoRePQALXfUjbPSvhoYuGBLOa5Kltp6z0mTUzhoZ BgwUDiBPdbYWA== From: Detlev Casanova To: linux-kernel@vger.kernel.org, Heiner Kallweit Cc: Andrew Lunn , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , netdev@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 2/2] net: phy: realtek: Add optional external PHY clock Date: Thu, 01 Jun 2023 14:53:02 -0400 Message-ID: <5682492.DvuYhMxLoT@arisu> In-Reply-To: <4a6c413c-8791-fd00-a73e-7a12413693e3@gmail.com> References: <20230531150340.522994-1-detlev.casanova@collabora.com> <20230531150340.522994-2-detlev.casanova@collabora.com> <4a6c413c-8791-fd00-a73e-7a12413693e3@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wednesday, May 31, 2023 3:08:53 P.M. EDT Heiner Kallweit wrote: > On 31.05.2023 17:03, Detlev Casanova wrote: > > In some cases, the PHY can use an external clock source instead of a > > crystal. > > > > Add an optional clock in the phy node to make sure that the clock source > > is enabled, if specified, before probing. > > > > Signed-off-by: Detlev Casanova > > --- > > > > drivers/net/phy/realtek.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c > > index 3d99fd6664d7..70c75dbbf799 100644 > > --- a/drivers/net/phy/realtek.c > > +++ b/drivers/net/phy/realtek.c > > @@ -12,6 +12,7 @@ > > > > #include > > #include > > #include > > > > +#include > > > > #define RTL821x_PHYSR 0x11 > > #define RTL821x_PHYSR_DUPLEX BIT(13) > > > > @@ -80,6 +81,7 @@ struct rtl821x_priv { > > > > u16 phycr1; > > u16 phycr2; > > bool has_phycr2; > > > > + struct clk *clk; > > > > }; > > > > static int rtl821x_read_page(struct phy_device *phydev) > > > > @@ -103,6 +105,11 @@ static int rtl821x_probe(struct phy_device *phydev) > > > > if (!priv) > > > > return -ENOMEM; > > > > + priv->clk = devm_clk_get_optional_enabled(dev, "xtal"); > > Why add priv->clk if it isn't used outside probe()? > > How about suspend/resume? Would it make sense to stop the clock > whilst PHY is suspended? I'm not sure about this. Isn't the clock still necessary when suspended for things like wake on lan ? > > + if (IS_ERR(priv->clk)) > > + return dev_err_probe(dev, PTR_ERR(priv->clk), > > + "failed to get phy xtal clock\n"); > > + > > > > ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1); > > if (ret < 0) > > > > return ret;