From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753404AbbLaON1 (ORCPT ); Thu, 31 Dec 2015 09:13:27 -0500 Received: from szxga03-in.huawei.com ([119.145.14.66]:28848 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751183AbbLaONX (ORCPT ); Thu, 31 Dec 2015 09:13:23 -0500 Subject: Re: [PATCH v1 3/3] ARM64 LPC: update binding doc To: Arnd Bergmann , Rongrong Zou References: <1451396032-23708-1-git-send-email-zourongrong@gmail.com> <1451396032-23708-4-git-send-email-zourongrong@gmail.com> <1899302.RWIn6Bg3Dr@wuerfel> CC: , , , , , , , From: Rongrong Zou Message-ID: <568537C3.3060902@huawei.com> Date: Thu, 31 Dec 2015 22:12:19 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <1899302.RWIn6Bg3Dr@wuerfel> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.177.30.66] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.568537CF.00D0,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: c8e66213a399bda3cc683539489bdf65 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Sorry for so late reply, it is difficult for me to understand ISA config :( . 在 2015/12/30 17:06, Arnd Bergmann 写道: > On Tuesday 29 December 2015 21:33:52 Rongrong Zou wrote: >> Signed-off-by: Rongrong Zou >> --- >> .../devicetree/bindings/arm64/low-pin-count.txt | 20 ++++++++++++++++++++ >> 1 file changed, 20 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm64/low-pin-count.txt >> >> diff --git a/Documentation/devicetree/bindings/arm64/low-pin-count.txt b/Documentation/devicetree/bindings/arm64/low-pin-count.txt >> new file mode 100644 >> index 0000000..215f2c4 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm64/low-pin-count.txt >> @@ -0,0 +1,20 @@ >> +Low Pin Count bus driver >> + >> +Usually LPC controller is part of PCI host bridge, so the legacy ISA >> +port locate on LPC bus can be accessed directly. But some SoC have >> +independent LPC controller, and we can access the legacy port by specifying >> +LPC address cycle. Thus, LPC driver is introduced. >> + >> +Required properties: >> +- compatible: "low-pin-count" >> +- reg: specifies low pin count address range >> + >> + >> +Example: >> + >> + lpc_0: lpc@a01b0000 { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + compatible = "low-pin-count"; >> + reg = <0x0 0xa01b0000 0x0 0x10000>; >> + }; > > One more thought: please try to stick as closely as possible to the existing > ISA binding that is documented at > > http://www.firmware.org/1275/bindings/isa/isa0_4d.ps From the specification, I think I should use 2 32bit integer to describe the isa addr in dts. > > In particular, this should cover the possibility of describing both memory > and I/O spaces in child devices. > I found below config in powerpc dts "arch/powerpc/boot/dts/mpc8544ds.dts" isa@1e { device_type = "isa"; #interrupt-cells = <2>; #size-cells = <1>; #address-cells = <2>; reg = <0xf000 0x0 0x0 0x0 0x0>; ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>; interrupt-parent = <&i8259>; rtc@70 { compatible = "pnpPNP,b00"; reg = <0x1 0x70 0x2>; }; the isa space in child-node: reg = <0x1 0x70 0x2>; 0x1 means IO space, 70 means addr, 0x2 is size. but when i config the following in dts, the ipmi_0 node can't be probed, I think there may be some problems. lpc_0: lpc@a01b0000 { compatible = "low-pin-count"; device_type = "isa"; #address-cells = <2>; #size-cells = <1>; reg = <0x0 0xa01b0000 0x0 0x10000>; ipmi_0:ipmi@000000e4{ device_type = "ipmi"; compatible = "ipmi-bt"; reg = <0x1 0x000000e4 0x4>; }; > Arnd > _______________________________________________ > linuxarm mailing list > linuxarm@huawei.com > http://rnd-openeuler.huawei.com/mailman/listinfo/linuxarm > >