[PATCH v14 0/7] fpga area and fpga bridge framework

[PATCH v14 0/7] fpga area and fpga bridge framework

[atull]

From: Alan Tull <atull@opensource.altera.com>

For v14 I'm dropping the concept of "simple-fpga-bus" for "fpga-area"
with reworked bindings.

An FPGA Area describes a section of an FPGA including the FPGA image needed to
program it and the hardware contained once it is programmed.  The intent is
to support Device Tree controlled programming of FPGA's.

Alan Tull (7):
  fpga: add usage documentation for fpga area
  fpga: add bindings document for fpga area
  add sysfs document for fpga bridge class
  ARM: socfpga: add bindings document for fpga bridge drivers
  fpga: add fpga bridge framework
  fpga: fpga-area: support device tree control for FPGA programming
  ARM: socfpga: fpga bridge driver support

 Documentation/ABI/testing/sysfs-class-fpga-bridge  |   11 +
 .../bindings/fpga/altera-fpga2sdram-bridge.txt     |   15 +
 .../bindings/fpga/altera-hps2fpga-bridge.txt       |   43 +++
 .../devicetree/bindings/fpga/fpga-area.txt         |   70 ++++
 Documentation/fpga/fpga-area.txt                   |  299 +++++++++++++++
 drivers/fpga/Kconfig                               |   21 ++
 drivers/fpga/Makefile                              |    7 +
 drivers/fpga/altera-fpga2sdram.c                   |  174 +++++++++
 drivers/fpga/altera-hps2fpga.c                     |  213 +++++++++++
 drivers/fpga/fpga-area.c                           |  313 ++++++++++++++++
 drivers/fpga/fpga-bridge.c                         |  388 ++++++++++++++++++++
 include/linux/fpga/fpga-bridge.h                   |   56 +++
 12 files changed, 1610 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-class-fpga-bridge
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-fpga2sdram-bridge.txt
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt
 create mode 100644 Documentation/devicetree/bindings/fpga/fpga-area.txt
 create mode 100644 Documentation/fpga/fpga-area.txt
 create mode 100644 drivers/fpga/altera-fpga2sdram.c
 create mode 100644 drivers/fpga/altera-hps2fpga.c
 create mode 100644 drivers/fpga/fpga-area.c
 create mode 100644 drivers/fpga/fpga-bridge.c
 create mode 100644 include/linux/fpga/fpga-bridge.h

-- 
1.7.9.5

Re: [PATCH v14 0/7] fpga area and fpga bridge framework

[Moritz Fischer]

Hi Alan,

On Thu, Dec 10, 2015 at 3:37 PM,  <atull@opensource.altera.com> wrote:
> From: Alan Tull <atull@opensource.altera.com>
>
> For v14 I'm dropping the concept of "simple-fpga-bus" for "fpga-area"
> with reworked bindings.

I had an offline discussion with Josh Cartwright about his concerns.
He brought up a good
point on w.r.t to the way FPGA Area (Bus) deals with things.

Currently we only support complete status = "okay" vs "disabled" kind
of overlays.

If now you have say a UART in the FPGA that you don't want to go away
and come back on reload,
we don't have a good way of expressing this. Is there a good way to
express non-mmio FPGA devices?

I've been toying around with hacking up struct device to include a
FPGA 'domain', and then, similar
to power domains allow devices to register suspend() / resume() style
callbacks (could call them pre_reload() or something like that ...)

I haven't gotten around to think it through. At this point it's just
an idea and I don't have real code to show.

I realize the issue with that is we'd have to make changes to struct device.

Cheers,

Moritz

Re: [PATCH v14 0/7] fpga area and fpga bridge framework

[Alan Tull]

On Mon, Dec 14, 2015 at 11:16 AM, Moritz Fischer
<moritz.fischer@ettus.com> wrote:
> Hi Alan,
>
> On Thu, Dec 10, 2015 at 3:37 PM,  <atull@opensource.altera.com> wrote:
>> From: Alan Tull <atull@opensource.altera.com>
>>
>> For v14 I'm dropping the concept of "simple-fpga-bus" for "fpga-area"
>> with reworked bindings.
>
> I had an offline discussion with Josh Cartwright about his concerns.
> He brought up a good
> point on w.r.t to the way FPGA Area (Bus) deals with things.
>
> Currently we only support complete status = "okay" vs "disabled" kind
> of overlays.
>
> If now you have say a UART in the FPGA that you don't want to go away
> and come back on reload,
> we don't have a good way of expressing this.

Maybe i don't understand what you are saying; could you write out a
sequence you want to be able to do?

If you want suspend/resume functionality that would reload the FPGA
after a suspend powers off the FPGA, that would be simple to add to
the FPGA area code and it wasn't a hack at all.

> Is there a good way to
> express non-mmio FPGA devices?

Is this a separate question/issue from the above?  Are you talking
about acceleration?

>
> I've been toying around with hacking up struct device to include a
> FPGA 'domain', and then, similar
> to power domains allow devices to register suspend() / resume() style
> callbacks (could call them pre_reload() or something like that ...)
>
> I haven't gotten around to think it through. At this point it's just
> an idea and I don't have real code to show.
>
> I realize the issue with that is we'd have to make changes to struct device.

That's interesting.  Usually a FPGA image has many devices in it, so
so way of making that dependency clear would be needed.  If any of the
devices involved are powered up, that FPGA image would need to be
loaded.

Currently I'm trying to get some bindings approved for doing device
tree control of loading the FPGA and probing the devices.  My idea is
that these bindings could be useful for some use cases where we are
loading hardware onto the FPGA that needs to show up in the device
tree. Some of Rob's feedback is that my proposal may be
Altera-specific. If the bindings that I am proposing are useful for at
least some uses with Xilinx parts, that would be valuable feedback at
this point.  If they are Altera-specific, then I may need to add
"altr," to some of the compatible strings like "altr,fpga-bus" and
"altr,fpga-area".  My original intent was to implement something that
you could use also, so I hope that's not the future here.

So my question for you is: is this stuff useful for you?

Alan Tull

>
> Cheers,
>
> Moritz

Re: [PATCH v14 0/7] fpga area and fpga bridge framework

[Moritz Fischer]

Hi Alan,

On Mon, Dec 14, 2015 at 5:56 PM, Alan Tull <delicious.quinoa@gmail.com> wrote:

>> I had an offline discussion with Josh Cartwright about his concerns.
>> He brought up a good
>> point on w.r.t to the way FPGA Area (Bus) deals with things.
>>
>> Currently we only support complete status = "okay" vs "disabled" kind
>> of overlays.

> Maybe i don't understand what you are saying; could you write out a
> sequence you want to be able to do?

Let's say you have a UART in the FPGA. You want to reprogram the FPGA
fabric that includes the UART (assuming proper resets etc happen)

1) Driver gets notified of impending doom, keeps hands off of FPGA
2) FPGA Manager reloads FPGA
3) FPGA Manager lets driver know FPGA is back
4) Driver can continue to function as always

It wouldn't even have to be a UART, on some boards simple SPI lines or UART
lines  go from the processor through the FPGA logic out to a pin.
When you reload the FPGA for a short moment of time that doesn't work,
while after the reload it works just fine. Maybe something like extcon could
be used for that?

> Is this a separate question/issue from the above?  Are you talking
> about acceleration?

I meant stuff like SPI that gets routed through the FPGA, sorry for
being unclear ;-)

>>
>> I've been toying around with hacking up struct device to include a
>> FPGA 'domain', and then, similar
>> to power domains allow devices to register suspend() / resume() style
>> callbacks (could call them pre_reload() or something like that ...)
>>
>> I haven't gotten around to think it through. At this point it's just
>> an idea and I don't have real code to show.
>>
>> I realize the issue with that is we'd have to make changes to struct device.
>
> That's interesting.  Usually a FPGA image has many devices in it, so
> so way of making that dependency clear would be needed.  If any of the
> devices involved are powered up, that FPGA image would need to be
> loaded.

Yeah. That's why I think the power domain model we have has a bunch of
similarities.

> Currently I'm trying to get some bindings approved for doing device
> tree control of loading the FPGA and probing the devices.  My idea is
> that these bindings could be useful for some use cases where we are
> loading hardware onto the FPGA that needs to show up in the device
> tree. Some of Rob's feedback is that my proposal may be
> Altera-specific. If the bindings that I am proposing are useful for at
> least some uses with Xilinx parts, that would be valuable feedback at
> this point.  If they are Altera-specific, then I may need to add
> "altr," to some of the compatible strings like "altr,fpga-bus" and
> "altr,fpga-area".  My original intent was to implement something that
> you could use also, so I hope that's not the future here.
>
> So my question for you is: is this stuff useful for you?

Definitely, I'm pretty happy with what you have so far!
I think the points I mentioned above apply to Altera devices, too.
Maybe we can solve this in two parts, and the first step is getting the
loading bindings accepted ;-)

Cheers,

Moritz

Re: [PATCH v14 0/7] fpga area and fpga bridge framework

[Jos Huisken]

On Thu, Dec 10, 2015 at 05:37:04PM -0600, atull@xxxxxxxxxxxxxxxxxxxxx wrote:
 >
 > For v14 I'm dropping the concept of "simple-fpga-bus" for "fpga-area"
 > with reworked bindings.

Works great (using 4.4rc5)!!
With:
- Pantelis' overlay patches and dtc,
- Walter Goossens' sopcinfo with minor overlay patch
- additional board_info.xml
- and some python scripting using pyfdt
Its -almost- possible to automatically generate a bitfile with 
appropriate overlay devicetree blob.
I only have an issue left w.r.t. phandles, I guess.

Using it now on de0-nano and veek kit.