From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753574AbcANKSp (ORCPT ); Thu, 14 Jan 2016 05:18:45 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1101 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753266AbcANKSS convert rfc822-to-8bit (ORCPT ); Thu, 14 Jan 2016 05:18:18 -0500 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 14 Jan 2016 02:19:41 -0800 Message-ID: <5697760C.1000901@nvidia.com> Date: Thu, 14 Jan 2016 18:18:52 +0800 From: Wei Ni User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Thierry Reding CC: , , , , Subject: Re: [PATCH V1 04/10] thermal: tegra: add T210-specific SOC_THERM driver References: <1452671929-32740-1-git-send-email-wni@nvidia.com> <1452671929-32740-5-git-send-email-wni@nvidia.com> <20160113150656.GD2588@ulmo> In-Reply-To: <20160113150656.GD2588@ulmo> X-Originating-IP: [10.19.224.146] X-ClientProxiedBy: HKMAIL101.nvidia.com (10.18.16.10) To HKMAIL101.nvidia.com (10.18.16.10) Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2016年01月13日 23:06, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Wed, Jan 13, 2016 at 03:58:43PM +0800, Wei Ni wrote: > [...] >> diff --git a/drivers/thermal/tegra/tegra_soctherm_fuse.c b/drivers/thermal/tegra/tegra_soctherm_fuse.c >> index 7c608698f1ae..22f402240672 100644 >> --- a/drivers/thermal/tegra/tegra_soctherm_fuse.c >> +++ b/drivers/thermal/tegra/tegra_soctherm_fuse.c >> @@ -28,6 +28,17 @@ >> #define FUSE_TSENSOR_COMMON 0x180 >> >> /* >> + * T210: Layout of bits in FUSE_TSENSOR_COMMON: >> + * 3 2 1 0 >> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 >> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ >> + * | BASE_FT | BASE_CP | SHFT_FT | SHIFT_CP | >> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ >> + * >> + * In chips prior to T210, this fuse was incorrectly sized as 26 bits, >> + * and didn't hold SHIFT_CP in [31:26]. Therefore these missing six bits > > The above diagram aso doesn't contain SHIFT_CP in bits [31:26] but > rather in bits [5:0]. Which one is correct: the text or the diagram? Hmm, sorry for the confusion. The diagram is for Tegra210, and the text is used to explain why the Tegra124 would use the FUSE_SPARE_REALIGNMENT_REG. For Tegra210, the FUSE_TSENSOR_COMMON contain four values, including SHIFT_CP in the bits of [5:0] But for Tegra124, the FUSE_TSENSOR_COMMON only contain three values, the SHIFT_CP is in the FUSE_SPARE_REALIGNMENT_REG which didn't be used in Tegra210. I will move the text under the line of "* T12x, etc: FUSE_TSENSOR_COMMON:", so that it will be more readable. > > Thierry > > * Unknown Key > * 0x7F3EB3A1 >