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From: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: <tony.luck@intel.com>, <tglx@linutronix.de>, <mingo@redhat.com>,
	<hpa@zytor.com>, <x86@kernel.org>, <linux-edac@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/5] x86/mcheck/AMD: Reduce number of blocks scanned per bank
Date: Thu, 14 Jan 2016 17:08:30 -0600	[thread overview]
Message-ID: <56982A6E.10000@amd.com> (raw)
In-Reply-To: <20160114225359.GL19941@pd.tnic>

On 1/14/2016 4:53 PM, Borislav Petkov wrote:
> On Thu, Jan 14, 2016 at 04:48:22PM -0600, Aravind Gopalakrishnan wrote:
>> True. But that BlkPtr logic also will undergo changes as it's interpretation
>> for future processors is different.
> But there still must be a bit there which says "this register is valid",
> like MCi_MISC[63].

There is a bit to say if it's valid or not.

> And so I'd very much prefer checking a bit (or bits) instead of relying
> on defines.
>
>

But we'd still need to know the last available MISC register for a bank 
to know when to end the loop right?

Currently we loop over all the possible blocks-
  for (block = 0; block < NR_BLOCKS; ++block) {
  <code>...

  increment block address;

  <code>..
  }

Here, we know we have to stop at block number 8 as that is the last MISC 
register that is present for a bank.
In the same manner, we'd still have to know the last possible MISC 
register for future processors..

Thanks,
-Aravind.

  reply	other threads:[~2016-01-14 23:08 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-14 22:05 [PATCH 0/5] Updates to AMD MCE driver per Scalable MCA spec Aravind Gopalakrishnan
2016-01-14 22:05 ` [PATCH 1/5] x86, mce: Fix order of AMD MCE init function call Aravind Gopalakrishnan
2016-01-14 22:05 ` [PATCH 2/5] x86/mcheck/AMD: Do not perform shared bank check for future processors Aravind Gopalakrishnan
2016-01-14 22:05 ` [PATCH 3/5] x86/mcheck/AMD: Reduce number of blocks scanned per bank Aravind Gopalakrishnan
2016-01-14 22:37   ` Borislav Petkov
2016-01-14 22:48     ` Aravind Gopalakrishnan
2016-01-14 22:53       ` Borislav Petkov
2016-01-14 23:08         ` Aravind Gopalakrishnan [this message]
2016-01-15 11:14           ` Borislav Petkov
2016-01-15 15:35             ` Gopalakrishnan, Aravind
2016-01-15 16:29             ` Aravind Gopalakrishnan
2016-01-14 22:05 ` [PATCH 4/5] x86/mcheck/AMD: Fix LVT offset configuration for thresholding Aravind Gopalakrishnan
2016-01-14 22:05 ` [PATCH 5/5] x86/mcheck/AMD: Set MCAX Enable bit Aravind Gopalakrishnan
2016-01-14 22:46   ` Borislav Petkov
2016-01-14 22:53     ` Aravind Gopalakrishnan
2016-01-14 22:58       ` Borislav Petkov
2016-01-14 23:13         ` Aravind Gopalakrishnan

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