From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935124AbcATEYN (ORCPT ); Tue, 19 Jan 2016 23:24:13 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:38354 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933721AbcATEYF (ORCPT ); Tue, 19 Jan 2016 23:24:05 -0500 MIME-version: 1.0 Content-type: text/plain; charset=utf-8 X-AuditID: cbfee690-f79646d000001316-be-569f0be20c8e Content-transfer-encoding: 8BIT Message-id: <569F0BE1.50801@samsung.com> Date: Wed, 20 Jan 2016 13:24:01 +0900 From: Jaehoon Chung User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 To: Shawn Lin , Ulf Hansson Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] mmc: dw_mmc: add hw_reset support References: <1452733682-3164-1-git-send-email-shawn.lin@rock-chips.com> In-reply-to: <1452733682-3164-1-git-send-email-shawn.lin@rock-chips.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpjkeLIzCtJLcpLzFFi42JZI2JSovuIe36YwfNj3BaXd81hszjyv5/R 4s6T9awWx9eGO7B43Lm2h83j76z9LB6fN8kFMEdx2aSk5mSWpRbp2yVwZczdPZWtoE+24s7l l2wNjE3iXYycHBICJhJ/lu5ih7DFJC7cW8/WxcjFISSwglHizdNnrDBFe2+uZodILGWUmLuu ixEkwSsgKPFj8j2WLkYODmYBeYkjl7IhTHWJKVNyIcofMEqcu7+VCaJcQ+Lary0sIDaLgKrE gzlnwRazCehIbP92HKxGVCBM4sG6vWB7RQT8JLbu2MoGYjMLWEv8/NEKFhcWsJSY8fI4mC0k 4C7RMGMvWA2ngIfEtqPfGUEWSwisY5f4/uYvG8QyAYlvkw+B3SkhICux6QAzxF+SEgdX3GCZ wCg2C8k3sxC+mYXwzQJG5lWMoqkFyQXFSelFJnrFibnFpXnpesn5uZsYgdFz+t+zCTsY7x2w PsQowMGoxMPL0DwvTIg1say4MvcQoynQDROZpUST84ExmlcSb2hsZmRhamJqbGRuaaYkzvta 6mewkEB6YklqdmpqQWpRfFFpTmrxIUYmDk6pBsYeIQmuv4//6s6Ubld/e93w3aYZlit/HMnx qL7g/8zqyuNagckFN89/cX1kOF/4X62Lw/56cbno37/KI/gZ+KbHSGQ/KCuqWhH3Kmjjikdv FCeH96s3MgoFRXKm1qvWH3J2MO/eYXkkyoZvzvauntRmHa9ct8AXv3k+SL0I1uCSjdKw4Th8 SImlOCPRUIu5qDgRADpYnXOZAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMIsWRmVeSWpSXmKPExsVy+t9jAd1H3PPDDFa/Z7a4vGsOm8WR//2M FneerGe1OL423IHF4861PWwef2ftZ/H4vEkugDmqgdEmIzUxJbVIITUvOT8lMy/dVsk7ON45 3tTMwFDX0NLCXEkhLzE31VbJxSdA1y0zB2ibkkJZYk4pUCggsbhYSd8O04TQEDddC5jGCF3f kCC4HiMDNJCwhjFj7u6pbAV9shV3Lr9ka2BsEu9i5OSQEDCR2HtzNTuELSZx4d56ti5GLg4h gaWMEnPXdTGCJHgFBCV+TL7H0sXIwcEsIC9x5FI2hKkuMWVKLkT5A0aJc/e3MkGUa0hc+7WF BcRmEVCVeDDnLNh8NgEdie3fjoPViAqESTxYt5cVxBYR8JPYumMrG4jNLGAt8fNHK1hcWMBS YsbL42C2kIC7RMOMvWA1nAIeEtuOfmecwCgwC8l1sxCum4Vw3QJG5lWMEqkFyQXFSem5hnmp 5XrFibnFpXnpesn5uZsYwRH6TGoH48Fd7ocYBTgYlXh4GZrnhQmxJpYVV+YeYpTgYFYS4T3C OT9MiDclsbIqtSg/vqg0J7X4EKMp0HsTmaVEk/OBySOvJN7Q2MTMyNLI3NDCyNhcSZy39lJk mJBAemJJanZqakFqEUwfEwenVAPjtm8FSyQ7fRKeuOl/k//Ia/U6UfHTminNpQm/ZJfKXnWW +qO5mFmP2bWM69oCp7fzjmTFTVL6kR32NmSJ2c+1r2+ErvVoNDrw87NLrdz943W94lIH924/ oCYp1R5/8uPEBboe81nFGS/piZwL8DwZmM0x5xRD5ot609lTz99cX6Swe8vfnzyPlViKMxIN tZiLihMBzlzNzOYCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Shawn. On 01/14/2016 10:08 AM, Shawn Lin wrote: > This patch implement hw_reset function for DesignWare > MMC controller. By adding this feature, mmc blk can > do some basic recovery. > > Set the following resets: > software reset – BMOD[0] for IDMAC only > DMA reset– CTRL[2] > FIFO reset – CTRL[1] bits > > Program the CARD_RESET register with a value of 0 for the bit > corresponding to the card number; This programming asserts the > RST_n signal and resets the card. After a minimum of 1 μs, de-asserts the > RST_n signal and takes the card out of reset. The application can program > a new CMD only after a minimum of 200 us > > This implementation can be easily tested by cutting off->On vmmc > while doing data accessing in background to simulate that case. > > Signed-off-by: Shawn Lin > > --- > > Changes in v3: > - reset for each slot > - simply the commit msg > > Changes in v2: > - remove unecessary mb > - reduce time cost for hw_reset > - combine SDMMC_CTRL_DMA_RESET and SDMMC_CTRL_FIFO_RESET > > drivers/mmc/host/dw_mmc.c | 29 +++++++++++++++++++++++++++++ > drivers/mmc/host/dw_mmc.h | 3 +++ > 2 files changed, 32 insertions(+) > > diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c > index 7128351..fddbcb6 100644 > --- a/drivers/mmc/host/dw_mmc.c > +++ b/drivers/mmc/host/dw_mmc.c > @@ -1477,6 +1477,34 @@ static int dw_mci_get_cd(struct mmc_host *mmc) > return present; > } > > +static void dw_mci_hw_reset(struct mmc_host *mmc) > +{ > + struct dw_mci_slot *slot = mmc_priv(mmc); > + struct dw_mci *host = slot->host; > + int reset; > + > + if (host->use_dma == TRANS_MODE_IDMAC) > + dw_mci_idmac_reset(host); > + > + if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | > + SDMMC_CTRL_FIFO_RESET)) > + return; > + > + /* > + * According to eMMC spec, card reset procedure: > + * tRstW >= 1us: RST_n pulse width > + * tRSCA >= 200us: RST_n to Command time > + * tRSTH >= 1us: RST_n high period > + */ > + reset = mci_readl(host, RST_N); > + reset &= ~(SDMMC_RST_HWACTIVE << slot->id); > + mci_writel(slot->host, RST_N, reset); I will pick this patch, after change "host" instead of "slot->host". (I will change it when i apply this.) Thanks! Best Regards, Jaehoon Chung > + usleep_range(1, 2); > + reset |= SDMMC_RST_HWACTIVE << slot->id; > + mci_writel(slot->host, RST_N, reset); > + usleep_range(200, 300); > +} > + > static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) > { > struct dw_mci_slot *slot = mmc_priv(mmc); > @@ -1563,6 +1591,7 @@ static const struct mmc_host_ops dw_mci_ops = { > .set_ios = dw_mci_set_ios, > .get_ro = dw_mci_get_ro, > .get_cd = dw_mci_get_cd, > + .hw_reset = dw_mci_hw_reset, > .enable_sdio_irq = dw_mci_enable_sdio_irq, > .execute_tuning = dw_mci_execute_tuning, > .card_busy = dw_mci_card_busy, > diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h > index f695b58..a14b7fc 100644 > --- a/drivers/mmc/host/dw_mmc.h > +++ b/drivers/mmc/host/dw_mmc.h > @@ -46,6 +46,7 @@ > #define SDMMC_VERID 0x06c > #define SDMMC_HCON 0x070 > #define SDMMC_UHS_REG 0x074 > +#define SDMMC_RST_N 0x078 > #define SDMMC_BMOD 0x080 > #define SDMMC_PLDMND 0x084 > #define SDMMC_DBADDR 0x088 > @@ -169,6 +170,8 @@ > #define SDMMC_IDMAC_ENABLE BIT(7) > #define SDMMC_IDMAC_FB BIT(1) > #define SDMMC_IDMAC_SWRESET BIT(0) > +/* H/W reset */ > +#define SDMMC_RST_HWACTIVE 0x1 > /* Version ID register define */ > #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) > /* Card read threshold */ >