From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754031AbcAYBPv (ORCPT ); Sun, 24 Jan 2016 20:15:51 -0500 Received: from regular1.263xmail.com ([211.150.99.139]:47651 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751763AbcAYBPs (ORCPT ); Sun, 24 Jan 2016 20:15:48 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: jay.xu@rock-chips.com X-FST-TO: keescook@google.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: jay.xu@rock-chips.com X-UNIQUE-TAG: <6685d96eb9ba2a1da91176def616848e> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v3 3/9] ASoC: rockchip: i2s: add support for grabbing output clock to codec To: Mark Brown , Sonny Rao References: <1452865796-23527-1-git-send-email-wxt@rock-chips.com> <1452865796-23527-4-git-send-email-wxt@rock-chips.com> <20160115174623.GZ6588@sirena.org.uk> <20160122171815.GD6588@sirena.org.uk> Cc: Caesar Wang , Heiko Stuebner , "open list:ARM/Rockchip SoC..." , leozwang@google.com, "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Kees Cook From: Jianqun Xu Message-ID: <56A57733.8020200@rock-chips.com> Date: Mon, 25 Jan 2016 09:15:31 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20160122171815.GD6588@sirena.org.uk> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mark ÔÚ 23/01/2016 01:18, Mark Brown дµÀ: > On Fri, Jan 15, 2016 at 01:48:04PM -0800, Sonny Rao wrote: >> On Fri, Jan 15, 2016 at 9:46 AM, Mark Brown wrote: > >>> If the I2S block is providing a clock to the CODEC then that's what the >>> software should do so that the CODEC can gate and ungate the clock as >>> required. This patch has the I2S block using a clock, not providing >>> one. > >> From my read of the clock diagram for RK3288 there is a single clock >> signal (labeled "clk_i2s0") that comes out of a fractional divider, >> and it is split such that one path gets sent to the I2S block and the >> second path is sent to a mux after which that signal is sent to an >> external pin that goes to the codec. > >> There are separate clock gates for the two paths: one for the I2S >> block and one after that mux before the external pin. > >> I'm not sure if it's being modeled that way in the Linux code or not, >> but at least physically I don't think this clock signal actually goes >> through the I2S block before being sent to the codec. > > That's not really the issue here, the issue is that it's not the I2S > controller that is consuming the clock so it should not be the I2S > controller driver that ensures that the clock is enabled. The driver > that manages the clock should be the one that uses it, like I say this > means you should add the code to enable the clock to the CODEC driver if > the CODEC driver needs the clock enabled. > Agree, now we almost use the simple-card for the CODEC driver, so I think we should enable the mclk(i2s-outclk) in the simple-card driver, is it ? I found a subnode property from simple-card document: - mclk-fs : Multiplication factor between stream rate and codec mclk, applied only for the dai-link. But the property responsible to the factor, not care if the mclk source clock is enabled or not. So does the simple-card driver can add support to enable/disable mclk ? >> Does that help clarify? > > The problem here isn't a lack of clarity in the situation. >