From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754336AbcBICfq (ORCPT ); Mon, 8 Feb 2016 21:35:46 -0500 Received: from mail.kernel.org ([198.145.29.136]:55377 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752462AbcBICfn (ORCPT ); Mon, 8 Feb 2016 21:35:43 -0500 Cc: vz@mleia.com, mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel , yamada.masahiro@socionext.com From: Dinh Nguyen Subject: commit 5146e0b05963 is causing a kernel crash on SoCFPGA X-Enigmail-Draft-Status: N1110 To: sboyd@codeaurora.org Message-ID: <56B9507B.9000201@kernel.org> Date: Mon, 8 Feb 2016 20:35:39 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Stephen, It appears that commit 5146e0b05966 "clk: simplify __clk_init_parent()" that is currently in linux-next is causing the following kernel crash on SoCFGPA[1]. I have bisected to this commit and doing a revert of the commit fixes the issue. Dinh [1] Linux version 4.5.0-rc2-next-20160208 (dinguyen@linux-builds1) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) ) #15 SMP Mon Feb 8 16:45:49 CST 2016 CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache Machine model: Altera SOCFPGA Cyclone V SoC Development Kit Truncating RAM at 0x00000000-0x40000000 to -0x30000000 Consider using a HIGHMEM enabled kernel. Memory policy: Data cache writealloc On node 0 totalpages: 196608 free_area_init_node: node 0, pgdat c06b2180, node_mem_map ef9fb000 Normal zone: 1536 pages used for memmap Normal zone: 0 pages reserved Normal zone: 196608 pages, LIFO batch:31 PERCPU: Embedded 13 pages/cpu @ef9ce000 s21888 r8192 d23168 u53248 pcpu-alloc: s21888 r8192 d23168 u53248 alloc=13*4096 pcpu-alloc: [0] 0 [0] 1 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 195072 Kernel command line: root=/dev/nfs rw nfsroot=137.57.160.210:/home/dinguyen/rootfs_yocto ip=dhcp PID hash table entries: 4096 (order: 2, 16384 bytes) Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) Memory: 772276K/786432K available (4851K kernel code, 283K rwdata, 1368K rodata, 336K init, 134K bss, 14156K reserved, 0K cma-reserved) Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xffc00000 - 0xfff00000 (3072 kB) vmalloc : 0xf0800000 - 0xff800000 ( 240 MB) lowmem : 0xc0000000 - 0xf0000000 ( 768 MB) modules : 0xbf000000 - 0xc0000000 ( 16 MB) .text : 0xc0008000 - 0xc061b12c (6221 kB) .init : 0xc061c000 - 0xc0670000 ( 336 kB) .data : 0xc0670000 - 0xc06b6d34 ( 284 kB) .bss : 0xc06b6d34 - 0xc06d87f4 ( 135 kB) SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 Hierarchical RCU implementation. Build-time adjustment of leaf fanout to 32. NR_IRQS:16 nr_irqs:16 16 L2C-310 enabling early BRESP for Cortex-A9 L2C-310 full line of zeros enabled for Cortex-A9 L2C-310 ID prefetch enabled, offset 1 lines L2C-310 dynamic clock gating enabled, standby mode enabled L2C-310 cache controller enabled, 8 ways, 512 kB L2C-310: CACHE_ID 0x410030c9, AUX_CTRL 0x76060001 ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at kernel/time/clockevents.c:44 cev_delta2ns+0x130/0x14c() Modules linked in: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.5.0-rc2-02373-g023bbb2 #15 Hardware name: Altera SOCFPGA [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0x74/0x90) [] (dump_stack) from [] (warn_slowpath_common+0x78/0xb4) [] (warn_slowpath_common) from [] (warn_slowpath_null+0x1c/0x24) [] (warn_slowpath_null) from [] (cev_delta2ns+0x130/0x14c) [] (cev_delta2ns) from [] (dw_apb_clockevent_init+0x7c/0x170) [] (dw_apb_clockevent_init) from [] (dw_apb_timer_init+0x70/0x158) [] (dw_apb_timer_init) from [] (clocksource_probe+0x48/0x8c) [] (clocksource_probe) from [] (start_kernel+0x260/0x384) [] (start_kernel) from [<0000807c>] (0x807c) ---[ end trace cb88537fdc8fa200 ]--- Division by zero in kernel. CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 4.5.0-rc2-02373-g023bbb2 #15 Hardware name: Altera SOCFPGA [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0x74/0x90) [] (dump_stack) from [] (Ldiv0_64+0x8/0x18) [] (Ldiv0_64) from [] (clocks_calc_max_nsecs+0x24/0x78) [] (clocks_calc_max_nsecs) from [] (__clocksource_update_freq_scale+0x1a0/0x2c0) [] (__clocksource_update_freq_scale) from [] (__clocksource_register_scale+0xc/0x48) [] (__clocksource_register_scale) from [] (dw_apb_timer_init+0xc4/0x158) [] (dw_apb_timer_init) from [] (clocksource_probe+0x48/0x8c) [] (clocksource_probe) from [] (start_kernel+0x260/0x384) [] (start_kernel) from [<0000807c>] (0x807c) clocksource: timer1: mask: 0xffffffff max_cycles: 0x0, max_idle_ns: 0 ns Division by zero in kernel. CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 4.5.0-rc2-02373-g023bbb2 #15 Hardware name: Altera SOCFPGA [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0x74/0x90) [] (dump_stack) from [] (Ldiv0_64+0x8/0x18) [] (Ldiv0_64) from [] (clocks_calc_mult_shift+0x11c/0x124) [] (clocks_calc_mult_shift) from [] (sched_clock_register+0x5c/0x1f0) [] (sched_clock_register) from [] (dw_apb_timer_init+0x110/0x158) [] (dw_apb_timer_init) from [] (clocksource_probe+0x48/0x8c) [] (clocksource_probe) from [] (start_kernel+0x260/0x384) [] (start_kernel) from [<0000807c>] (0x807c) Division by zero in kernel. CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 4.5.0-rc2-02373-g023bbb2 #15 Hardware name: Altera SOCFPGA [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0x74/0x90) [] (dump_stack) from [] (Ldiv0_64+0x8/0x18) [] (Ldiv0_64) from [] (clocks_calc_max_nsecs+0x24/0x78) [] (clocks_calc_max_nsecs) from [] (sched_clock_register+0xac/0x1f0) [] (sched_clock_register) from [] (dw_apb_timer_init+0x110/0x158) [] (dw_apb_timer_init) from [] (clocksource_probe+0x48/0x8c) [] (clocksource_probe) from [] (start_kernel+0x260/0x384) [] (start_kernel) from [<0000807c>] (0x807c) sched_clock: 32 bits at 0 Hz, resolution 0ns, wraps every 0ns Division by zero in kernel. CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 4.5.0-rc2-02373-g023bbb2 #15 Hardware name: Altera SOCFPGA [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0x74/0x90) [] (dump_stack) from [] (Ldiv0_64+0x8/0x18) [] (Ldiv0_64) from [] (clocks_calc_mult_shift+0x11c/0x124) [] (clocks_calc_mult_shift) from [] (register_current_timer_delay+0x2c/0x114) [] (register_current_timer_delay) from [] (dw_apb_timer_init+0x124/0x158) [] (dw_apb_timer_init) from [] (clocksource_probe+0x48/0x8c) [] (clocksource_probe) from [] (start_kernel+0x260/0x384) [] (start_kernel) from [<0000807c>] (0x807c)