From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932284AbcBIJTa (ORCPT ); Tue, 9 Feb 2016 04:19:30 -0500 Received: from mail-cys01nam02on0067.outbound.protection.outlook.com ([104.47.37.67]:43492 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752530AbcBIJTZ (ORCPT ); Tue, 9 Feb 2016 04:19:25 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; ni.com; dkim=none (message not signed) header.d=none;ni.com; dmarc=bestguesspass action=none header.from=xilinx.com; Subject: Re: [PATCH 0/2] ARM: zynq: address silent L2 cache corruption To: Josh Cartwright , Michal Simek , =?UTF-8?Q?S=c3=b6ren_Brinkmann?= References: CC: Russell King , , , Gratian Crisan From: Michal Simek Message-ID: <56B9AF14.3070706@xilinx.com> Date: Tue, 9 Feb 2016 10:19:16 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22120.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(164054003)(24454002)(199003)(189002)(230700001)(19300405004)(83506001)(65816999)(4326007)(5001770100001)(36756003)(23746002)(92566002)(5001960100002)(106466001)(11100500001)(50986999)(50466002)(2950100001)(4001350100001)(2906002)(1220700001)(77096005)(86362001)(54356999)(65806001)(65956001)(47776003)(63266004)(87936001)(15975445007)(4001450100002)(189998001)(19580395003)(33656002)(586003)(1096002)(76176999)(87266999)(6806005)(5008740100001)(107986001)(562404015);DIR:OUT;SFP:1101;SCL:1;SRVR:BL2NAM02HT242;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;MLV:sfv;A:1;MX:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: 43bc07b5-1710-405b-494d-08d331321944 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:BL2NAM02HT242; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(13017025)(8121501046)(13018025)(13015025)(13023025)(13024025)(5005006)(10201501046)(3002001);SRVR:BL2NAM02HT242;BCL:0;PCL:0;RULEID:;SRVR:BL2NAM02HT242; X-Forefront-PRVS: 08476BC6EF X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Feb 2016 09:19:22.9528 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT242 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3.2.2016 03:30, Josh Cartwright wrote: > The Zynq has a bug where the L2 cache will return invalid data in some > circumstances unless the L2C_RAM register is set to 0x20202 before the first > enabling of the L2 cache. > > The Xilinx-recommended solution to this problem is to ensure that early one of > the earlier bootstages correctly initialize L2C_RAM, however, this issue wasn't > discovered and fixed until after their EDK/SDK 14.4 release. For systems built > prior to that, and which lack field-upgradable bootloaders, this issue still > exists and silent data corruption can be seen in the wild. > > Fix these systems by ensuring L2C_RAM is properly initialized at the > earliest convenient moment prior to the L2 being brought up, which is > when the SLCR is first mapped. > > Unfortunately, there isn't much public documentation on exactly what the > L2C_RAM register is for, or how it is used, only that software is responsible > for initializing it to the proper value prior to bringing up L2. > > You can find more information about this bug in AR#54190[1]. > > 1: http://www.xilinx.com/support/answers/54190.html > > Josh Cartwright (2): > ARM: zynq: initialize slcr mapping earlier > ARM: zynq: address L2 cache data corruption > > arch/arm/mach-zynq/common.c | 3 +-- > arch/arm/mach-zynq/slcr.c | 4 ++++ > 2 files changed, 5 insertions(+), 2 deletions(-) > Applied both. Thanks, Michal