From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756559AbcBINiV (ORCPT ); Tue, 9 Feb 2016 08:38:21 -0500 Received: from mail-wm0-f45.google.com ([74.125.82.45]:38629 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755100AbcBINiU (ORCPT ); Tue, 9 Feb 2016 08:38:20 -0500 Subject: Re: [PATCH v3 2/3] clocksource: Add NPS400 timers driver To: Noam Camus , "linux-kernel@vger.kernel.org" References: <1454418899-25500-1-git-send-email-noamc@ezchip.com> <1454775406-25277-3-git-send-email-noamc@ezchip.com> <56B8A482.8040302@linaro.org> Cc: "linux-snps-arc@lists.infradead.org" , "marc.zyngier@arm.com" , Chris Metcalf , Tal Zilcer , Gilad Ben Yossef , Rob Herring , Thomas Gleixner , John Stultz From: Daniel Lezcano Message-ID: <56B9EBC7.4010703@linaro.org> Date: Tue, 9 Feb 2016 14:38:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux i686; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/09/2016 01:36 PM, Noam Camus wrote: >> From: Daniel Lezcano [mailto:daniel.lezcano@linaro.org] Sent: >> Monday, February 08, 2016 4:22 PM > >>> + ret = clk_prepare_enable(clk); + if (ret) + pr_err("Couldn't >>> enable parent clock\n"); + + nps_timer_rate = clk_get_rate(clk); > >> If there is an error, you continue the execution of the code. I >> guess you expect the system to hang in any case with the error in >> the >console, right ? > > Since our clock is root then returned value will always be valid. I > am far from being expert here, but no one checks for clk_get_rate() > return value for error. Could you refer to a single place at > clocksource drivers that checks for error in the return value. Actually I was referring to clk_prepare_enable, clocksource_register_hz. Agree clk_get_rate is always valid. >>> + ret = clocksource_register_hz(clksrc, nps_timer_rate); > >> You can simplify the driver even more by using >> clocksource_mmio_init. > Since my base address depends on cluster number, which CPU is part > of, this interface is not much of a use. On top of that it assumes > that I am little endian by using readl family accessories. Why can't you use ? clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick", nps_timer_rate, 32, nps_clksrc_read); -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog