From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753259AbcBKJJa (ORCPT ); Thu, 11 Feb 2016 04:09:30 -0500 Received: from foss.arm.com ([217.140.101.70]:52519 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753242AbcBKJJR (ORCPT ); Thu, 11 Feb 2016 04:09:17 -0500 Subject: Re: [PATCH 2/2] irqchip/gic: Only set the EOImodeNS bit for the root controller To: Jon Hunter , Thomas Gleixner , Jason Cooper References: <1455031497-14043-1-git-send-email-jonathanh@nvidia.com> <1455031497-14043-2-git-send-email-jonathanh@nvidia.com> Cc: linux-kernel@vger.kernel.org From: Marc Zyngier Organization: ARM Ltd Message-ID: <56BC4FBA.10801@arm.com> Date: Thu, 11 Feb 2016 09:09:14 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.5.0 MIME-Version: 1.0 In-Reply-To: <1455031497-14043-2-git-send-email-jonathanh@nvidia.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/02/16 15:24, Jon Hunter wrote: > EOImode1 is only used for the root controller and hence only the root > controller uses the eoimode1 functions for handling interrupts. However, > if the root controller supports EOImode1, then the EOImodeNS bit will be > set for all GICs, enabling EOImode1. This is not what we want and this > causes interrupts on non-root GICs to only be dropped in priority but > never deactivated. Therefore, only set the EOImodeNS bit for the root > controller. > > Signed-off-by: Jon Hunter Acked-by: Marc Zyngier M. -- Jazz is not dead. It just smells funny...