From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1948020AbcBSBF3 (ORCPT ); Thu, 18 Feb 2016 20:05:29 -0500 Received: from regular1.263xmail.com ([211.150.99.133]:41619 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1947496AbcBSBF1 (ORCPT ); Thu, 18 Feb 2016 20:05:27 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: jay.xu@rock-chips.com X-FST-TO: zhengxing@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: jay.xu@rock-chips.com X-UNIQUE-TAG: <0961882e0c785cf93e830b06af842c19> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH 5/6] dt-bindings: add documentation of rk3399 clock controller To: Heiko Stuebner References: <1455673992-16469-1-git-send-email-jay.xu@rock-chips.com> <20160218143648.GL9654@rob-hp-laptop> <56C6664F.8070600@rock-chips.com> <1758156.nKISImzkM9@phil> Cc: Rob Herring , pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, jwerner@chromium.org, broonie@kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, sboyd@codeaurora.org, linus.walleij@linaro.org, sjoerd.simons@collabora.co.uk, huangtao@rock-chips.com, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Xing Zheng From: Jianqun Xu Message-ID: <56C66A49.2080501@rock-chips.com> Date: Fri, 19 Feb 2016 09:05:13 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <1758156.nKISImzkM9@phil> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Heiko ÔÚ 19/02/2016 08:53, Heiko Stuebner дµÀ: > Am Freitag, 19. Februar 2016, 08:48:15 schrieb Jianqun Xu: >> Hi Rob >> >> ÔÚ 18/02/2016 22:36, Rob Herring дµÀ: >>> On Wed, Feb 17, 2016 at 09:54:49AM +0800, jianqun.xu wrote: >>>> From: Xing Zheng >>>> >>>> Add the devicetree binding for the cru on the rk3399 which quite >>>> similar structured as previous clock controllers. >>>> >>>> Signed-off-by: Xing Zheng >>>> --- >>>> >>>> .../bindings/clock/rockchip,rk3399-cru.txt | 82 >>>> ++++++++++++++++++++++ 1 file changed, 82 insertions(+) >>>> create mode 100644 >>>> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt>> >>>> diff --git >>>> a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >>>> b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new >>>> file mode 100644 >>>> index 0000000..07bcc6e >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >>>> @@ -0,0 +1,82 @@ >>>> +* Rockchip RK3399 Clock and Reset Unit >>> >>> [...] >>> >>>> +Example: General Register Files >>>> + >>>> + pmugrf: syscon@ff320000 { >>>> + compatible = "rockchip,rk3399-pmugrf", "syscon"; >>> >>> Is this documented? >> >> Since there is no documentation for rockchip grf from early SoCs, I >> think if we need to add a new devicetree documentation, such as >> Documentation/devicetree/bindings/clock/rockchip,rk3399-grf.txt ? > > The grf is not clock-specific, so the directory is probably not correct. > I'd think bindings/arm/rockchip/grf.txt might be better or > bindings/soc/rockchip/grf.txt or somewhere else. And define the properties > for all per-soc GRFs in there. > > In any case we really should add the missing grf binding documentation (in a > separate patch of course), as the grf is a pretty commonly used shared > component. > Got it, I will add bindings/soc/rockchip/grf.txt in next patch Thanks ! > >> >> If you agree, I will add it in next patch >> >>>> + reg = <0x0 0xff320000 0x0 0x1000>; >>>> + }; >>>> + >>>> + grf: syscon@ff770000 { >>>> + compatible = "rockchip,rk3399-grf", "syscon"; >>> >>> ditto. >>> >>>> + reg = <0x0 0xff770000 0x0 0x10000>; >>>> + }; >>>> + >>>> +Example: Clock controller node: >>>> + >>>> + pmucru: pmu-clock-controller@ff750000 { >>>> + compatible = "rockchip,rk3399-pmucru"; >>>> + reg = <0x0 0xff750000 0x0 0x1000>; >>>> + #clock-cells = <1>; >>>> + #reset-cells = <1>; >>>> + }; >>>> + >>>> + cru: clock-controller@ff760000 { >>>> + compatible = "rockchip,rk3399-cru"; >>>> + reg = <0x0 0xff760000 0x0 0x1000>; >>>> + rockchip,grf = <&grf>; >>>> + #clock-cells = <1>; >>>> + #reset-cells = <1>; >>>> + }; >>>> + >>>> +Example: UART controller node that consumes the clock generated by the >>>> clock + controller: >>>> + >>>> + uart0: serial@ff1a0000 { >>>> + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; >>>> + reg = <0x0 0xff180000 0x0 0x100>; >>>> + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; >>>> + clock-names = "baudclk", "apb_pclk"; >>>> + interrupts = ; >>>> + reg-shift = <2>; >>>> + reg-io-width = <4>; >>>> + }; >>>> -- >>>> 1.9.1 > > > >