From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757525AbcBWIrl (ORCPT ); Tue, 23 Feb 2016 03:47:41 -0500 Received: from mailout1.w1.samsung.com ([210.118.77.11]:30009 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757383AbcBWIri (ORCPT ); Tue, 23 Feb 2016 03:47:38 -0500 X-AuditID: cbfec7f5-f79b16d000005389-54-56cc1ca7355d Subject: Re: [PATCH] ARM: dts: add support for gpio buttons for exynos5422-odroidxu3 To: Anand Moon , Kukjin Kim , Javier Martinez Canillas , Marek Szyprowski References: <1456214467-3344-1-git-send-email-linux.amoon@gmail.com> <56CC167A.8040303@samsung.com> <56CC194F.6080905@samsung.com> Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org From: Krzysztof Kozlowski X-Enigmail-Draft-Status: N1110 Message-id: <56CC1CA3.7010803@samsung.com> Date: Tue, 23 Feb 2016 17:47:31 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-version: 1.0 In-reply-to: <56CC194F.6080905@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKLMWRmVeSWpSXmKPExsVy+t/xq7rLZc6EGWzcr2gx/8g5Vos3b9cw Wbx+YWjR//g1s8Wmx9dYLS7vmsNmMeP8PiaLdRtvsVusPXKX3YHTY+esu+wem1Z1snlsXlLv saUfyOvbsorR4/MmuQC2KC6blNSczLLUIn27BK6Mi5+vsRXcEK54eZGtgXGhQBcjJ4eEgInE 82cvGCFsMYkL99azdTFycQgJLGWU2Nm6hBXCecoosfv4K1aQKmGBMInDv3YwgSREBFYySmw6 epgFoqqFUeJS7wowh1mgnVHiztvZbCAtbALGEpuXL2GDWCIn0ds9iQXE5hXQkviy5Q7YchYB VYn7Dy+D2aICERKHO7vYIWoEJX5MvgdWzymgLfH523XmLkYOoAV6EvcvaoGEmQXkJTavecs8 gVFwFpKOWQhVs5BULWBkXsUomlqaXFCclJ5rpFecmFtcmpeul5yfu4kREhlfdzAuPWZ1iFGA g1GJh9fD63SYEGtiWXFl7iFGCQ5mJRFeB74zYUK8KYmVValF+fFFpTmpxYcYpTlYlMR5Z+56 HyIkkJ5YkpqdmlqQWgSTZeLglGpgDGPdkdM1xSfc+crFT3f2tZs9iHpf4MhcfLk18oDPvPWs C9SWRPQf7Sm9uq+8cuqfM9YJP6cdyZtXzxbNZHGx+EvRwg/5a9nsuK0MF1squk5n/5HD/0Io 5812w09+W+88FPC77HxgpkNwVXM+r3Zk1I5JM16s23D+1LPvgfuKHTIXzJe+E2A9UYmlOCPR UIu5qDgRAEWC07uIAgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23.02.2016 17:33, Krzysztof Kozlowski wrote: > On 23.02.2016 17:21, Krzysztof Kozlowski wrote: >> On 23.02.2016 17:01, Anand Moon wrote: >>> Add support for gpio-based button on Odroid-XU3 boards >>> for reboot/poweroff feature. >>> >>> Signed-off-by: Anand Moon >>> --- >>> changes rebase based on linux next-20160222. >>> >>> Tested on Odroid-XU4 >>> >>> dmesg output. >>> [ 3.286068] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/power_key[0]' - status (0) >>> [ 3.286206] gpio-11 (power key): gpiod_set_debounce: missing set() or set_debounce() operations >>> [ 3.286600] input: gpio_keys as /devices/platform/gpio_keys/input/input0 >>> --- >>> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 22 ++++++++++++++++++++++ >>> 1 file changed, 22 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> index 1bd507b..db9770b 100644 >>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >>> @@ -11,6 +11,7 @@ >>> */ >>> >>> #include >>> +#include >>> #include >>> #include >>> #include >>> @@ -54,6 +55,22 @@ >>> #cooling-cells = <2>; >>> cooling-levels = <0 130 170 230>; >>> }; >>> + >>> + gpio_keys { >>> + compatible = "gpio-keys"; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&gpio_power_key>; >>> + >>> + power_key { >>> + interrupt-parent = <&gpx0>; >>> + interrupts = <3 IRQ_TYPE_NONE>; >> >> Hmmm.... why you specify the interrupts? >> >>> + gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; > > Please, explain it to me. The SW2 key is connected to PWRON of PMIC. > However you are adding a GPIO key for external interrupt source 3 > (XE.INT3)... which comes from PMIC's ONOB. > > It's interesting.... how does it work? The PMIC will generate ONOB > interrupt on PWRON low->high change (when PWRHOLD is high)? Hmmm... This is not well documented but apparently that is the case. The PMIC will generate ONOB interrupt (with 16 ms de-bounce for PWRON) on each PWRON flip. This looks kind of hacky or indirect usage. Using a GPIO key not for GPIO itself but for an interrupt generated by PMIC on a key press... Best regards, Krzysztof