From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752578AbcBWLIz (ORCPT ); Tue, 23 Feb 2016 06:08:55 -0500 Received: from mail-sn1nam02on0065.outbound.protection.outlook.com ([104.47.36.65]:37690 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750914AbcBWLIw (ORCPT ); Tue, 23 Feb 2016 06:08:52 -0500 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; google.com; dkim=none (message not signed) header.d=none;google.com; dmarc=bestguesspass action=none header.from=xilinx.com; Subject: Re: [PATCH V4 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver To: Bharat Kumar Gogada , Bjorn Helgaas , , , , , , , , , , , , , References: <1455208091-15556-1-git-send-email-bharatku@xilinx.com> <1455208091-15556-6-git-send-email-bharatku@xilinx.com> CC: , , , , "Bharat Kumar Gogada" , Ravi Kiran Gummaluri From: Michal Simek Message-ID: <56CC3DB2.3080900@xilinx.com> Date: Tue, 23 Feb 2016 12:08:34 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <1455208091-15556-6-git-send-email-bharatku@xilinx.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22148.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(24454002)(199003)(164054003)(189002)(87936001)(63266004)(50986999)(76176999)(54356999)(87266999)(65816999)(11100500001)(6806005)(5001960100002)(23746002)(189998001)(107886002)(4001430100002)(36756003)(2201001)(65956001)(86362001)(59896002)(47776003)(230700001)(1220700001)(4326007)(1096002)(586003)(5008740100001)(2906002)(50466002)(92566002)(83506001)(2950100001)(64126003)(33656002)(65806001)(77096005)(106466001)(19580395003)(19580405001)(80316001)(4001350100001)(36386004)(5001770100001)(41533002)(921003)(107986001)(83996005)(2101003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:BL2NAM02HT188;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;MLV:sfv;A:1;MX:1;LANG:en; X-MS-Office365-Filtering-Correlation-Id: 891a968d-61dc-4c9e-98c3-08d33c41b53e X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:BL2NAM02HT188; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(192813158149592); X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(5005006)(8121501046)(13015025)(13018025)(13024025)(13023025)(13017025)(10201501046)(3002001);SRVR:BL2NAM02HT188;BCL:0;PCL:0;RULEID:;SRVR:BL2NAM02HT188; X-Forefront-PRVS: 08617F610C X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2016 11:08:49.8191 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.100];Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT188 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11.2.2016 17:28, Bharat Kumar Gogada wrote: > This patch does required modifications to microblaze PCI subsystem, to > work with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze > and Zynq. > > Signed-off-by: Bharat Kumar Gogada > Signed-off-by: Ravi Kiran Gummaluri > --- > Changes: > Removed pcibios_get_phb_of_node in pci-common.c, using generic version > instead. > Modified pcibios_fixup_bus in pci-common.c, as per generic architecuture. > Modified pcibios_align_resource in pci-common.c, as per generic > architecuture, removed temporary variable. > Removed pci_domain_nr in pci-common.c, instead using generic code. > Added pcibios_add_device in pci-common.c, as per generic architecuture. > Adding Kernel configuration in arch/microblaze as required for generic PCI > domains. > Added kernel configuration for driver to support Microblaze. > --- > arch/microblaze/Kconfig | 3 +++ > arch/microblaze/pci/pci-common.c | 56 +++++++--------------------------------- > drivers/pci/host/Kconfig | 2 +- > 3 files changed, 14 insertions(+), 47 deletions(-) > > diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig > index 0bce820..c3702b9 100644 > --- a/arch/microblaze/Kconfig > +++ b/arch/microblaze/Kconfig > @@ -271,6 +271,9 @@ config PCI > config PCI_DOMAINS > def_bool PCI > > +config PCI_DOMAINS_GENERIC > + def_bool PCI_DOMAINS > + > config PCI_SYSCALL > def_bool PCI > > diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c > index ae838ed..35654be 100644 > --- a/arch/microblaze/pci/pci-common.c > +++ b/arch/microblaze/pci/pci-common.c > @@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t address) > } > EXPORT_SYMBOL_GPL(pci_address_to_pio); > > -/* > - * Return the domain number for this bus. > - */ > -int pci_domain_nr(struct pci_bus *bus) > -{ > - struct pci_controller *hose = pci_bus_to_host(bus); > - > - return hose->global_number; > -} > -EXPORT_SYMBOL(pci_domain_nr); > - > /* This routine is meant to be used early during boot, when the > * PCI bus numbers have not yet been assigned, and you need to > * issue PCI config cycles to an OF device. > @@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus *bus) > > void pcibios_fixup_bus(struct pci_bus *bus) > { > - /* When called from the generic PCI probe, read PCI<->PCI bridge > - * bases. This is -not- called when generating the PCI tree from > - * the OF device-tree. > - */ > - if (bus->self != NULL) > - pci_read_bridge_bases(bus); > - > - /* Now fixup the bus bus */ > - pcibios_setup_bus_self(bus); > - > - /* Now fixup devices on that bus */ > - pcibios_setup_bus_devices(bus); > + /* nothing to do */ > } > EXPORT_SYMBOL(pcibios_fixup_bus); > > -static int skip_isa_ioresource_align(struct pci_dev *dev) > -{ > - return 0; > -} > - > /* > * We need to avoid collisions with `mirrored' VGA ports > * and other strange ISA hardware, so we always want the > @@ -899,20 +872,18 @@ static int skip_isa_ioresource_align(struct pci_dev *dev) > resource_size_t pcibios_align_resource(void *data, const struct resource *res, > resource_size_t size, resource_size_t align) > { > - struct pci_dev *dev = data; > - resource_size_t start = res->start; > - > - if (res->flags & IORESOURCE_IO) { > - if (skip_isa_ioresource_align(dev)) > - return start; > - if (start & 0x300) > - start = (start + 0x3ff) & ~0x3ff; > - } > - > - return start; > + return res->start; > } > EXPORT_SYMBOL(pcibios_align_resource); > > +int pcibios_add_device(struct pci_dev *dev) > +{ > + dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); > + > + return 0; > +} > +EXPORT_SYMBOL(pcibios_add_device); > + > /* > * Reparent resource children of pr that conflict with res > * under res, and make res replace those children. > @@ -1333,13 +1304,6 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose, > (unsigned long)hose->io_base_virt - _IO_BASE); > } > > -struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) > -{ > - struct pci_controller *hose = bus->sysdata; > - > - return of_node_get(hose->dn); > -} > - > static void pcibios_scan_phb(struct pci_controller *hose) > { > LIST_HEAD(resources); > diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig > index d5e58ba..7c56c2e 100644 > --- a/drivers/pci/host/Kconfig > +++ b/drivers/pci/host/Kconfig > @@ -79,7 +79,7 @@ config PCI_KEYSTONE > > config PCIE_XILINX > bool "Xilinx AXI PCIe host bridge support" > - depends on ARCH_ZYNQ > + depends on ARCH_ZYNQ || MICROBLAZE > help > Say 'Y' here if you want kernel to support the Xilinx AXI PCIe > Host Bridge driver. > Less code in arch is better. Acked-by: Michal Simek Bjorn: Please take this via your tree. Thanks, Michal