From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751611AbcBZB4r (ORCPT ); Thu, 25 Feb 2016 20:56:47 -0500 Received: from szxga02-in.huawei.com ([119.145.14.65]:42523 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750880AbcBZB4p (ORCPT ); Thu, 25 Feb 2016 20:56:45 -0500 Subject: Re: [PATCH v9 2/6] clk: hisilicon: add CRG driver for hi3519 soc To: Stephen Boyd References: <1456127280-23275-1-git-send-email-xuejiancheng@huawei.com> <1456127280-23275-3-git-send-email-xuejiancheng@huawei.com> <20160225234215.GK28849@codeaurora.org> CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , From: xuejiancheng Message-ID: <56CFB051.3050809@huawei.com> Date: Fri, 26 Feb 2016 09:54:25 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:38.0) Gecko/20100101 Thunderbird/38.5.0 MIME-Version: 1.0 In-Reply-To: <20160225234215.GK28849@codeaurora.org> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.217.211] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.56CFB065.0039,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 7a526ddabe53f6206be6d7821fdba71b Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Stephen, Thank you for your advice. I'll fixed them in next version. Regards, Jiancheng. On 2016/2/26 7:42, Stephen Boyd wrote: > On 02/22, Jiancheng Xue wrote: >> diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hi3519-crg.txt >> new file mode 100644 >> index 0000000..2d23950 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/hi3519-crg.txt >> @@ -0,0 +1,46 @@ >> +Example: CRG nodes >> +CRG: clock-reset-controller@12010000 { >> + compatible = "hisilicon,hi3519-crg"; > > Indentation is off here. > >> + reg = <0x12010000 0x10000>; >> + #clock-cells = <1>; >> + #reset-cells = <2>; >> +}; >> + >> +Example: consumer nodes >> +i2c0: i2c@12110000 { >> + compatible = "hisilicon,hi3519-i2c"; >> + reg = <0x12110000 0x1000>; >> + clocks = <&CRG HI3519_I2C0_RST>;*/ >> + resets = <&CRG 0xe4 0>; >> +}; >> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig >> index e434854..296371f 100644 >> --- a/drivers/clk/hisilicon/Kconfig >> +++ b/drivers/clk/hisilicon/Kconfig >> @@ -1,3 +1,11 @@ >> +config COMMON_CLK_HI3519 >> + tristate "Hi3519 Clock Driver" >> + depends on ARCH_HISI || COMPILE_TEST >> + select RESET_HISI >> + default y > > default ARCH_HISI > >> + help >> + Build the clock driver for hi3519. >> + >> diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c >> new file mode 100644 >> index 0000000..50e00e7 >> --- /dev/null >> +++ b/drivers/clk/hisilicon/reset.c >> + >> +int hisi_reset_init(struct device_node *np) >> +{ >> + struct hisi_reset_controller *rstc; >> + >> + rstc = kzalloc(sizeof(*rstc), GFP_KERNEL); >> + if (!rstc) >> + return -ENOMEM; >> + >> + rstc->membase = of_iomap(np, 0); > > Any reason why we can't pass the platform device here and map the > register space with platform device APIs? > >> + if (!rstc->membase) >> + return -EINVAL; >> + >> + spin_lock_init(&rstc->lock); >> + >> + rstc->rcdev.owner = THIS_MODULE; >> + rstc->rcdev.ops = &hisi_reset_ops; >> + rstc->rcdev.of_node = np; >> + rstc->rcdev.of_reset_n_cells = 2; >> + rstc->rcdev.of_xlate = hisi_reset_of_xlate; >> + >> + return reset_controller_register(&rstc->rcdev); >> +} >> +EXPORT_SYMBOL(hisi_reset_init); > > Why not GPL? >