From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423554AbcBZWVa (ORCPT ); Fri, 26 Feb 2016 17:21:30 -0500 Received: from p02c11o142.mxlogic.net ([208.65.144.75]:51374 "EHLO p02c11o142.mxlogic.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755532AbcBZWVZ convert rfc822-to-8bit (ORCPT ); Fri, 26 Feb 2016 17:21:25 -0500 X-Greylist: delayed 522 seconds by postgrey-1.27 at vger.kernel.org; Fri, 26 Feb 2016 17:21:25 EST X-MXL-Hash: 56d0cfe5501b9d89-d5eb396e112776f290c3db0aa24cdd8b0cfbc715 X-MXL-Hash: 56d0cdd90fb721c4-92569f7038f12e6a8d1190ed00765e9e2cb58a21 From: Kevin Smith To: Vivien Didelot , Andrew Lunn CC: "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "kernel@savoirfairelinux.com" , "David S. Miller" , Florian Fainelli , Sergei Shtylyov , Guenter Roeck , Neil Armstrong , Sascha Hauer , Russell King Subject: Re: [PATCH net-next 7/9] net: dsa: mv88e6xxx: restore VLANTable map control Thread-Topic: [PATCH net-next 7/9] net: dsa: mv88e6xxx: restore VLANTable map control Thread-Index: AQHRcMHqCp0O6NhAkk+MbjRlX7JmWJ8/MEwAgAAFSYCAAAlQgIAACbyA Date: Fri, 26 Feb 2016 22:12:28 +0000 Message-ID: <56D0CDCD.2040806@elecsyscorp.com> References: <1456510568-13679-1-git-send-email-vivien.didelot@savoirfairelinux.com> <1456510568-13679-8-git-send-email-vivien.didelot@savoirfairelinux.com> <56D0B964.4090002@elecsyscorp.com> <20160226210419.GA1560@lunn.ch> <87d1rj6tlo.fsf@ketchup.mtl.sfl> In-Reply-To: <87d1rj6tlo.fsf@ketchup.mtl.sfl> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.63.192.142] Content-Type: text/plain; charset="Windows-1252" Content-ID: <5EBAF73B792B1640B3CB60A9D2B96579@dciincorporated.com> Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-AnalysisOut: [v=2.1 cv=f4xOcbGM c=1 sm=1 tr=0 a=51qEjsKpZkmECDgIwGerrA==] X-AnalysisOut: [:117 a=51qEjsKpZkmECDgIwGerrA==:17 a=Ubgksy_53ZIA:10 a=N65] X-AnalysisOut: [9UExz7-8A:10 a=xqWC_Br6kY4A:10 a=jFJIQSaiL_oA:10 a=We-sAYu] X-AnalysisOut: [8CWrxnJP6SJoA:9 a=pILNOxqGKmIA:10] X-Spam: [F=0.5000000000; CM=0.500; MH=0.500(2016022614); S=0.200(2015072901)] X-MAIL-FROM: X-SOURCE-IP: [64.198.156.98] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Vivien, Andrew, On 02/26/2016 03:37 PM, Vivien Didelot wrote: > Here, 5 is the CPU port and 6 is a DSA port. > > After joining ports 0, 1, 2 in the same bridge, we end up with: > > Port 0 1 2 3 4 5 6 > 0 - * * - - * * > 1 * - * - - * * > 2 * * - - - * * > 3 - - - - - * * > 4 - - - - - * * > 5 * * * * * - * > 6 * * * * * * - The case I am concerned about is if the switch connected over DSA in this example has a WAN port on it, which can legitimately route to the CPU on port 5 but should not route to the LAN ports 0, 1, and 2. Does this VLAN allow direct communication between the WAN and LAN? Or is this prevented by DSA or some other mechanism? Thanks, Kevin