From: Sergey Fedorov <serge.fdrv@gmail.com>
To: paulmck@linux.vnet.ibm.com
Cc: linux-kernel@vger.kernel.org
Subject: Re: Documentation/memory-barriers.txt: How can READ_ONCE() and WRITE_ONCE() provide cache coherence?
Date: Sat, 27 Feb 2016 23:13:00 +0300 [thread overview]
Message-ID: <56D2034C.4010803@gmail.com> (raw)
In-Reply-To: <20160226213133.GI3522@linux.vnet.ibm.com>
On 27.02.2016 00:31, Paul E. McKenney wrote:
> Without READ_ONCE(), common sub-expression elimination optimizations
> can cause later reads of a given variable to see older value than
> previous reads did. For a (silly) example:
>
> a = complicated_pure_function(x);
> b = x;
> c = complicated_pure_function(x);
>
> The compiler is within its rights to transform this into the following:
>
> a = complicated_pure_function(x);
> b = x;
> c = a(x);
>
> In this case, the assignment to b might see a newer value of x than did
> the later assignment to c. This violates cache coherence, which states
> that all reads from a given variable must agree on the order of values
> taken on by that variable.
I see how READ_ONCE() and WRITE_ONCE() can prevent compiler from
speculating on variable values and optimizing memory accesses. But
concerning cache coherency itself, my understanding is that software can
really ensure hardware cache coherency by using one of the following
methods:
- by not using the caches
- by using some sort of cache maintenance instructions
- by using hardware cache coherency mechanisms (which is what normally
used)
What kind of "cache coherency" do you mean?
Thanks,
Sergey
next prev parent reply other threads:[~2016-02-27 20:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-26 21:14 Documentation/memory-barriers.txt: How can READ_ONCE() and WRITE_ONCE() provide cache coherence? Sergey Fedorov
2016-02-26 21:31 ` Paul E. McKenney
2016-02-27 20:13 ` Sergey Fedorov [this message]
2016-02-27 22:53 ` Paul E. McKenney
2016-02-29 19:07 ` Sergey Fedorov
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