From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752946AbcB2THY (ORCPT ); Mon, 29 Feb 2016 14:07:24 -0500 Received: from mail-lf0-f45.google.com ([209.85.215.45]:36695 "EHLO mail-lf0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751053AbcB2THW (ORCPT ); Mon, 29 Feb 2016 14:07:22 -0500 Subject: Re: Documentation/memory-barriers.txt: How can READ_ONCE() and WRITE_ONCE() provide cache coherence? To: paulmck@linux.vnet.ibm.com References: <56D0C02D.6000905@gmail.com> <20160226213133.GI3522@linux.vnet.ibm.com> <56D2034C.4010803@gmail.com> <20160227225347.GV3522@linux.vnet.ibm.com> Cc: linux-kernel@vger.kernel.org From: Sergey Fedorov Message-ID: <56D496E6.6060206@gmail.com> Date: Mon, 29 Feb 2016 22:07:18 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <20160227225347.GV3522@linux.vnet.ibm.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28.02.2016 01:53, Paul E. McKenney wrote: > On Sat, Feb 27, 2016 at 11:13:00PM +0300, Sergey Fedorov wrote: >> On 27.02.2016 00:31, Paul E. McKenney wrote: >>> Without READ_ONCE(), common sub-expression elimination optimizations >>> can cause later reads of a given variable to see older value than >>> previous reads did. For a (silly) example: >>> >>> a = complicated_pure_function(x); >>> b = x; >>> c = complicated_pure_function(x); >>> >>> The compiler is within its rights to transform this into the following: >>> >>> a = complicated_pure_function(x); >>> b = x; >>> c = a(x); >>> >>> In this case, the assignment to b might see a newer value of x than did >>> the later assignment to c. This violates cache coherence, which states >>> that all reads from a given variable must agree on the order of values >>> taken on by that variable. >> I see how READ_ONCE() and WRITE_ONCE() can prevent compiler from >> speculating on variable values and optimizing memory accesses. But >> concerning cache coherency itself, my understanding is that software >> can really ensure hardware cache coherency by using one of the >> following methods: >> - by not using the caches >> - by using some sort of cache maintenance instructions >> - by using hardware cache coherency mechanisms (which is what >> normally used) >> >> What kind of "cache coherency" do you mean? > All current systems supporting Linux guarantee that volatile accesses > to a given single variable will be seen in order, even when caches are > active, and without using any cache-coherence instructions. Note "a > given single variable". If there is more than one variable in play, > explicit memory ordering is required. The "volatile" is also important, > because the compiler (and in a few cases, the hardware) can reorder > non-volatile accesses. Thank you for clarification. I think this was a bit confusing for me because I always think of cache coherence independent from high-level C objects like variables. For me, cache coherence is the behavior of system in response to CPU(s) making load/store operations to the same memory location. Thanks, Sergey