From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753160AbcCIAwT (ORCPT ); Tue, 8 Mar 2016 19:52:19 -0500 Received: from regular1.263xmail.com ([211.150.99.133]:43448 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753199AbcCIAvu (ORCPT ); Tue, 8 Mar 2016 19:51:50 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: jay.xu@rock-chips.com X-FST-TO: elaine.zhang@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: jay.xu@rock-chips.com X-UNIQUE-TAG: <3d670bfa99ffe444a943b5758e1cbdeb> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [RESEND PATCH v2 5/5] clk: rockchip: add clock controller for the RK3399 To: Doug Anderson , Xing Zheng References: <1456827275-8035-1-git-send-email-zhengxing@rock-chips.com> <1456827322-8130-1-git-send-email-zhengxing@rock-chips.com> Cc: =?UTF-8?Q?Heiko_St=c3=bcbner?= , Michael Turquette , Stephen Boyd , "linux-kernel@vger.kernel.org" , linux-clk , "linux-arm-kernel@lists.infradead.org" , "open list:ARM/Rockchip SoC..." , Tao Huang , elaine.zhang@rock-chips.com From: Jianqun Xu Message-ID: <56DF7393.4020600@rock-chips.com> Date: Wed, 9 Mar 2016 08:51:31 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Doug: ÔÚ 09/03/2016 07:34, Doug Anderson дµÀ: > Xing Zheng, > > On Tue, Mar 1, 2016 at 2:15 AM, Xing Zheng wrote: >> + MMC(SCLK_SDMMC_DRV, "emmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), >> + MMC(SCLK_SDMMC_SAMPLE, "emmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), > > Can you and Jianqun Xu please coordinate? Though I don't have a TRM > for rk3399 and I haven't looked through this whole patch, I know for > sure there's a problem when I pick the latest patch series from both > of you it doesn't compile. > > I believe this is the latest from each of you in patchwork: > > 8462411 [v3,1/3] dt-bindings: add bindings for rk3399 clock controller > 8462431 [v3,2/3] clk: rockchip: add dt-binding header for rk3399 > 8462441 [v3,3/3] ARM64: dts: rockchip: add core dtsi file for rk3399 > > 8463741 [RESEND,v2,1/5] clk: rockchip: add more mux parameters for > new pll sources > 8463801 [RESEND,v2,2/5] clk: rockchip: Add support for multiple > clock providers > 8463771 [RESEND,v2,3/5] clk: rockchip: add new pll-type for rk3399 > and similar socs > 8463781 [RESEND,v2,4/5] clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type > 8463831 [RESEND,v2,5/5] clk: rockchip: add clock controller for the RK3399 > > > Specifically your patch from March 1st refers to SCLK_SDMMC_DRV and > SCLK_SDMMC_SAMPLE. Those defines existed in Jianqun Xu's patch back > on Feb 19th , but his > latest patch series from March 1st > no longer has those > #defines. > > Can you two resolve this so I can pick both patch series and see that > they compile? ...or let me know where I messed up, of course. > ok, we will upload dtsi later after the clk-rk3399 driver been applied. xing will send the patches for rk3399 together. We hope the dtsi could be applied first but depends on clk driver, but it seems not a good idea, we will resend dtsi patch after more drivers are applied. Thanks Doug. > Thanks! > > -Doug > > >