Re: [PATCH 3/3] infiniband: IB/hns: add Hisilicon RoCE support with bindings

[Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>]

Hello.

On 3/11/2016 1:37 PM, Lijun Ou wrote:

> This submit add binding file and dts file.

    I see no .dts file.

>
> Signed-off-by: Lijun Ou <oulijun@huawei.com>
> Signed-off-by: Wei Hu(Xavier) <xavier.huwei@huawei.com>
> ---
>   .../bindings/infiniband/hisilicon-hns-roce.txt     | 68 ++++++++++++++++++++++
>   1 file changed, 68 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt
>
> diff --git a/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt b/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt
> new file mode 100644
> index 0000000..8004641
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt
> @@ -0,0 +1,68 @@
> +HiSilicon RoCE DT description
> +
> +HiSilicon RoCE engine is a part of network subsystem.
> +It works depending on other part of network wubsytem, such as, gmac and

    Subsystem.

> +dsa fabric.
> +
> +Additional properties are described here:
> +
> +Required properties:
> +- compatible: Should contain "hisilicon,hns-roce-v1".
> +- reg: Physical base address of the roce driver and
> +length of memory mapped region.
> +- eth-handle: phandle, specifies a reference to a node
> +representing a ethernet device.
> +- dsaf-handle: phandle, specifies a reference to a node
> +representing a dsaf device.
> +- #address-cells: must be 2
> +- #size-cells: must be 2
> +Optional properties:
> +- dma-coherent: Present if DMA operations are coherent.
> +- interrupt-parent: the interrupt parent of this device.
> +- interrupts: should contain 32 completion event irq,1 async event irq
> +and 1 event overflow irq.

    The "interrupt-names" prop is strongly desired with some many IRQs.

> +Example:
> +	rocee@0xc4000000 {

    The node names should be generic, not implementation specific.

[...]

MBR, Sergei