From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751966AbcCXXjg (ORCPT ); Thu, 24 Mar 2016 19:39:36 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:36274 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750859AbcCXXje (ORCPT ); Thu, 24 Mar 2016 19:39:34 -0400 MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 X-AuditID: cbfee691-f79766d0000012b6-a8-56f47ab3c540 Content-transfer-encoding: 8BIT Message-id: <56F47AB3.2070007@samsung.com> Date: Fri, 25 Mar 2016 08:39:31 +0900 From: Chanwoo Choi User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 To: k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: jh80.chung@samsung.com, andi.shyti@samsung.com, inki.dae@samsung.com, sw0312.kim@samsung.com, pankaj.dubey@samsung.com, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 2/8] clk: samsung: exynos3250: Add UART2 clock References: <1458027490-13787-1-git-send-email-cw00.choi@samsung.com> <1458027490-13787-3-git-send-email-cw00.choi@samsung.com> In-reply-to: <1458027490-13787-3-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHIsWRmVeSWpSXmKPExsWyRsSkUHdz1Zcwg4anGhbbjzxjtZh/5Byr xaT7E1gsbvxqY7V4/cLQov/xa2aLTY+vsVpc3jWHzWLG+X1MFou2fmG3OPymndVixuSXbBar dv1hdOD12DnrLrvHplWdbB6bl9R79G1ZxejxeZNcAGsUl01Kak5mWWqRvl0CV8aGh49YCr7I VWy6fI2tgXGWZBcjJ4eEgInEytO3WCFsMYkL99azdTFycQgJrGCUeLTwE1MXIwdY0eTtxhDx WYwSS3o+gzXwCghK/Jh8jwWkhllAXuLIpWyQMLOAusSkeYuYIeofMEr8+v0eql5L4uj7CWA2 i4CqxPa9D5lBbDag+P4XN9hA5ogKREh0n6gECYsIxElMvHgD7B5mgWYmibtrVjGBJIQFXCVa z+2HOrSRUeL39FZGkASngJvE+Xf3GEESEgKNHBJf175ggtgmIPFt8iEWiG9kJTYdYIb4WFLi 4IobLBMYxWYh+WcWwj+zkPyzgJF5FaNoakFyQXFSepGpXnFibnFpXrpecn7uJkZgtJ7+92zi Dsb7B6wPMQpwMCrx8Dq4fwkTYk0sK67MPcRoCnTERGYp0eR8YErIK4k3NDYzsjA1MTU2Mrc0 UxLn1ZH+GSwkkJ5YkpqdmlqQWhRfVJqTWnyIkYmDU6qBMVDg4eXYXbKPzhwNNGJyW9hwfJLg 62n5Z1nnVEzey5fZ8XtHqctlyyP2i7PrX/7m/v2lK1HT4rLAlPMy4VeMlho9nxo9+4p2wQLr fSkKxc1v3fe8f88hxzxV9uyCwHgXN7dO87ebetZIdG/eLL88+H9H3c4tvv77yxTP6R8/KRpl mZoh/l61TomlOCPRUIu5qDgRABOxVvjRAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmleLIzCtJLcpLzFFi42I5/e+xoO7mqi9hBp2blCy2H3nGajH/yDlW i0n3J7BY3PjVxmrx+oWhRf/j18wWmx5fY7W4vGsOm8WM8/uYLBZt/cJucfhNO6vFjMkv2SxW 7frD6MDrsXPWXXaPTas62Tw2L6n36NuyitHj8ya5ANaoBkabjNTElNQihdS85PyUzLx0WyXv 4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKAblRTKEnNKgUIBicXFSvp2mCaEhrjpWsA0 Ruj6hgTB9RgZoIGENYwZGx4+Yin4Ilex6fI1tgbGWZJdjBwcEgImEpO3G3cxcgKZYhIX7q1n 62Lk4hASmMUosaTnMytIgldAUOLH5HssIPXMAvISRy5lg4SZBdQlJs1bxAxR/4BR4tfv91D1 WhJH308As1kEVCW2733IDGKzAcX3v7jBBjJHVCBCovtEJUhYRCBOYuLFG2B7mQWamSTurlnF BJIQFnCVaD23H+qgRkaJ39NbGUESnAJuEuff3WOcwAh0JsJ9sxDum4XkvgWMzKsYJVILkguK k9JzjfJSy/WKE3OLS/PS9ZLzczcxghPCM+kdjId3uR9iFOBgVOLhfeHyJUyINbGsuDL3EKME B7OSCK9WNFCINyWxsiq1KD++qDQntfgQoynQgxOZpUST84HJKq8k3tDYxMzI0sjc0MLI2FxJ nPfx/3VhQgLpiSWp2ampBalFMH1MHJxSDYx5m6Q+3pgnxXik4fwTgQUSLtFzUx6xtGT+2D87 4ZjlLvEzly4vP7TftGLzMd1gY7a0K8vnHHbWsQ7bd3lW9gvjjbuPMn3UYjbdezLyTfo1a7bP IQrRCrZv3ebdmMr5tfnhrCKGK6s2Xglcsinnhlfc+q/mTok1r9bN/JbRaD/p6vNnan4cKrej lFiKMxINtZiLihMB198eUB4DAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Ping. Hi Sylwester, Could you review this patch? Regards, Chanwoo Choi On 2016년 03월 15일 16:38, Chanwoo Choi wrote: > From: Pankaj Dubey > > This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC. > > Cc: Sylwester Nawrocki > Cc: Tomasz Figa > Signed-off-by: Pankaj Dubey > Signed-off-by: Chanwoo Choi > Reviewed-by: Krzysztof Kozlowski > --- > drivers/clk/samsung/clk-exynos3250.c | 6 ++++++ > include/dt-bindings/clock/exynos3250.h | 6 +++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c > index fdd41b17a24f..bc60e399d1bc 100644 > --- a/drivers/clk/samsung/clk-exynos3250.c > +++ b/drivers/clk/samsung/clk-exynos3250.c > @@ -306,6 +306,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), > > /* SRC_PERIL0 */ > + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4), > MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4), > MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4), > > @@ -390,6 +391,7 @@ static struct samsung_div_clock div_clks[] __initdata = { > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), > > /* DIV_PERIL0 */ > + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), > DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), > > @@ -552,6 +554,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = { > GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre", > GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0), > + > + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", > + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", > GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", > @@ -649,6 +654,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { > GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0), > GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0), > GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0), > + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0), > GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0), > GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0), > }; > diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h > index 63d01c15d2b3..ddb874130d86 100644 > --- a/include/dt-bindings/clock/exynos3250.h > +++ b/include/dt-bindings/clock/exynos3250.h > @@ -79,6 +79,7 @@ > #define CLK_MOUT_CORE 58 > #define CLK_MOUT_APLL 59 > #define CLK_MOUT_ACLK_266_SUB 60 > +#define CLK_MOUT_UART2 61 > > /* Dividers */ > #define CLK_DIV_GPL 64 > @@ -127,6 +128,7 @@ > #define CLK_DIV_CORE 107 > #define CLK_DIV_HPM 108 > #define CLK_DIV_COPY 109 > +#define CLK_DIV_UART2 110 > > /* Gates */ > #define CLK_ASYNC_G3D 128 > @@ -223,6 +225,7 @@ > #define CLK_BLOCK_MFC 219 > #define CLK_BLOCK_CAM 220 > #define CLK_SMIES 221 > +#define CLK_UART2 222 > > /* Special clocks */ > #define CLK_SCLK_JPEG 224 > @@ -249,12 +252,13 @@ > #define CLK_SCLK_SPI0 245 > #define CLK_SCLK_UART1 246 > #define CLK_SCLK_UART0 247 > +#define CLK_SCLK_UART2 248 > > /* > * Total number of clocks of main CMU. > * NOTE: Must be equal to last clock ID increased by one. > */ > -#define CLK_NR_CLKS 248 > +#define CLK_NR_CLKS 249 > > /* > * CMU DMC >