From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752118AbcCXXjs (ORCPT ); Thu, 24 Mar 2016 19:39:48 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:34612 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750949AbcCXXjm (ORCPT ); Thu, 24 Mar 2016 19:39:42 -0400 MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 X-AuditID: cbfee68e-f793c6d00000136c-a0-56f47abcbe38 Content-transfer-encoding: 8BIT Message-id: <56F47ABC.7060006@samsung.com> Date: Fri, 25 Mar 2016 08:39:40 +0900 From: Chanwoo Choi User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 To: k.kozlowski@samsung.com, kgene@kernel.org, s.nawrocki@samsung.com, tomasz.figa@gmail.com Cc: jh80.chung@samsung.com, andi.shyti@samsung.com, inki.dae@samsung.com, sw0312.kim@samsung.com, pankaj.dubey@samsung.com, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 3/8] clk: samsung: exynos3250: Add MMC2 clock References: <1458027490-13787-1-git-send-email-cw00.choi@samsung.com> <1458027490-13787-4-git-send-email-cw00.choi@samsung.com> In-reply-to: <1458027490-13787-4-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPIsWRmVeSWpSXmKPExsWyRsSkWHdP1ZcwgzstehbbjzxjtZh/5Byr xaT7E1gsbvxqY7V4/cLQov/xa2aLTY+vsVpc3jWHzWLG+X1MFou2fmG3OPymndVixuSXbBar dv1hdOD12DnrLrvHplWdbB6bl9R79G1ZxejxeZNcAGsUl01Kak5mWWqRvl0CV8bCXWeZC77L V+y7cIWpgbFdqouRk0NCwESiu+cII4QtJnHh3nq2LkYuDiGBFYwScz6vZIYp2vLpOSNEYimj xNqfl8A6eAUEJX5MvsfSxcjBwSwgL3HkUjZImFlAXWLSvEXMEPUPGCXWH13OBFGvJbHjyQIw m0VAVWLTjNcsIDYbUHz/ixtsIHNEBSIkuk9UgoRFBOIkJl68AXYQs0Azk8TdNavAeoUFXCS+ LZwMtaCRUWLhqWtsIAlOATeJk53bwS6VEGjkkDi/9xMLxDYBiW+TD4FdKiEgK7HpANRnkhIH V9xgmcAoNgvJP7MQ/pmF5J8FjMyrGEVTC5ILipPSi4z0ihNzi0vz0vWS83M3MQLj9fS/Z307 GG8esD7EKMDBqMTD+8LlS5gQa2JZcWXuIUZToCMmMkuJJucDk0JeSbyhsZmRhamJqbGRuaWZ kjhvgtTPYCGB9MSS1OzU1ILUovii0pzU4kOMTBycUg2M1mbuE9xrz/dJ9k8uNLav7ma4NlFs dzW3wPcl4n5hNp8fR888PTF48/PwIuGw/Us1nSfIPOmQNT0RoVB67b/gtq4Y1eSYaZ6vq5dk aRzy8LWT231p6+0Lc8V+RswoCni459SZTdtDQ07tu6j10NQ5wjW5x6uxIDerYemDy1v6FaOc On1m2lQqsRRnJBpqMRcVJwIAa+cpotICAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphleLIzCtJLcpLzFFi42I5/e+xgO6eqi9hBpcOq1lsP/KM1WL+kXOs FpPuT2CxuPGrjdXi9QtDi/7Hr5ktNj2+xmpxedccNosZ5/cxWSza+oXd4vCbdlaLGZNfslms 2vWH0YHXY+esu+wem1Z1snlsXlLv0bdlFaPH501yAaxRDYw2GamJKalFCql5yfkpmXnptkre wfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUA3KimUJeaUAoUCEouLlfTtME0IDXHTtYBp jND1DQmC6zEyQAMJaxgzFu46y1zwXb5i34UrTA2M7VJdjJwcEgImEls+PWeEsMUkLtxbz9bF yMUhJLCUUWLtz0tgCV4BQYkfk++xdDFycDALyEscuZQNEmYWUJeYNG8RM0T9A0aJ9UeXM0HU a0nseLIAzGYRUJXYNOM1C4jNBhTf/+IGG8gcUYEIie4TlSBhEYE4iYkXb4DtZRZoZpK4u2YV WK+wgIvEt4WToRY0MkosPHWNDSTBKeAmcbJzO+MERoFZSO6bhXDfLCT3LWBkXsUokVqQXFCc lJ5rmJdarlecmFtcmpeul5yfu4kRnBKeSe1gPLjL/RCjAAejEg+vg/uXMCHWxLLiytxDjBIc zEoivFrRQCHelMTKqtSi/Pii0pzU4kOMpkAPTmSWEk3OB6arvJJ4Q2MTMyNLI3NDCyNjcyVx 3sf/14UJCaQnlqRmp6YWpBbB9DFxcEo1MG5OtpA8yvlPWDHugdC2i9/jO333/Nw6p7BSwe/g Y7atq+/PdpmzfOWWqzPydJX26XVm6mxZOG3l0dezWaZxtnbPPDK57sOpLwKpHucZ3VROKE/n 5tTxuuHN+Elr4T5m3ljFJreNF0I5H8yIcVv8SMFM8cqihCv29pMfi/PPf+H3W0W9TyrjSKgS S3FGoqEWc1FxIgBc9AuhHwMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Ping. Hi Sylwester, Could you review this patch? Regards, Chanwoo Choi On 2016년 03월 15일 16:38, Chanwoo Choi wrote: > This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC. > > Cc: Sylwester Nawrocki > Cc: Tomasz Figa > Signed-off-by: Chanwoo Choi > Reviewed-by: Krzysztof Kozlowski > --- > drivers/clk/samsung/clk-exynos3250.c | 9 +++++++++ > include/dt-bindings/clock/exynos3250.h | 7 ++++++- > 2 files changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c > index bc60e399d1bc..16575ee874cb 100644 > --- a/drivers/clk/samsung/clk-exynos3250.c > +++ b/drivers/clk/samsung/clk-exynos3250.c > @@ -302,6 +302,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = { > > /* SRC_FSYS */ > MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4), > + MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4), > MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4), > MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), > > @@ -390,6 +391,11 @@ static struct samsung_div_clock div_clks[] __initdata = { > CLK_SET_RATE_PARENT, 0), > DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), > > + /* DIV_FSYS2 */ > + DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8, > + CLK_SET_RATE_PARENT, 0), > + DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), > + > /* DIV_PERIL0 */ > DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), > DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), > @@ -540,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = { > GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi", > GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0), > + GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre", > + GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre", > GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), > GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre", > @@ -635,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { > GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0), > GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0), > GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0), > + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0), > GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0), > GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0), > GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0), > diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h > index ddb874130d86..c796ff02ceeb 100644 > --- a/include/dt-bindings/clock/exynos3250.h > +++ b/include/dt-bindings/clock/exynos3250.h > @@ -80,6 +80,7 @@ > #define CLK_MOUT_APLL 59 > #define CLK_MOUT_ACLK_266_SUB 60 > #define CLK_MOUT_UART2 61 > +#define CLK_MOUT_MMC2 62 > > /* Dividers */ > #define CLK_DIV_GPL 64 > @@ -129,6 +130,8 @@ > #define CLK_DIV_HPM 108 > #define CLK_DIV_COPY 109 > #define CLK_DIV_UART2 110 > +#define CLK_DIV_MMC2_PRE 111 > +#define CLK_DIV_MMC2 112 > > /* Gates */ > #define CLK_ASYNC_G3D 128 > @@ -226,6 +229,7 @@ > #define CLK_BLOCK_CAM 220 > #define CLK_SMIES 221 > #define CLK_UART2 222 > +#define CLK_SDMMC2 223 > > /* Special clocks */ > #define CLK_SCLK_JPEG 224 > @@ -253,12 +257,13 @@ > #define CLK_SCLK_UART1 246 > #define CLK_SCLK_UART0 247 > #define CLK_SCLK_UART2 248 > +#define CLK_SCLK_MMC2 249 > > /* > * Total number of clocks of main CMU. > * NOTE: Must be equal to last clock ID increased by one. > */ > -#define CLK_NR_CLKS 249 > +#define CLK_NR_CLKS 250 > > /* > * CMU DMC >