From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753894AbcC1DZs (ORCPT ); Sun, 27 Mar 2016 23:25:48 -0400 Received: from regular1.263xmail.com ([211.150.99.133]:35393 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753492AbcC1DZp (ORCPT ); Sun, 27 Mar 2016 23:25:45 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: zhengxing@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhengxing@rock-chips.com X-UNIQUE-TAG: <961ef06f45ed622df5bc6bb3413b9bbf> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <56F8A3FF.6090800@rock-chips.com> Date: Mon, 28 Mar 2016 11:24:47 +0800 From: Xing Zheng User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120410 Thunderbird/11.0.1 MIME-Version: 1.0 To: Heiko Stuebner CC: linux-rockchip@lists.infradead.org, huangtao@rock-chips.com, jay.xu@rock-chips.com, elaine.zhang@rock-chips.com, dianders@chromium.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller References: <1458974276-10325-1-git-send-email-zhengxing@rock-chips.com> <1458974276-10325-3-git-send-email-zhengxing@rock-chips.com> <1507551.YPleCY5ZQt@phil> <3689505.b0IKY6iWOt@phil> In-Reply-To: <3689505.b0IKY6iWOt@phil> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Heiko, On 2016年03月28日 08:07, Heiko Stuebner wrote: > Hi Xing, > > Am Montag, 28. März 2016, 01:52:12 schrieb Heiko Stübner: >> Am Samstag, 26. März 2016, 14:37:54 schrieb Xing Zheng: >>> Add devicetree bindings for Rockchip cru which found on >>> Rockchip SoCs. >>> >>> Signed-off-by: Xing Zheng >>> Signed-off-by: Jianqun Xu >>> Acked-by: Rob Herring >>> --- >>> >>> Changes in v5: None >>> Changes in v3: None >>> Changes in v2: None >>> >>> .../bindings/clock/rockchip,rk3399-cru.txt | 83 >>> >>> ++++++++++++++++++++ 1 file changed, 83 insertions(+) >>> >>> create mode 100644 >>> >>> Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >>> >>> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399- >> cru.txt >> >>> b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt new >>> file mode 100644 >>> index 0000000..9427caa >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt >>> @@ -0,0 +1,83 @@ >>> +* Rockchip RK3399 Clock and Reset Unit >>> + >>> +The RK3399 clock controller generates and supplies clock to various >>> +controllers within the SoC and also implements a reset controller for >>> SoC +peripherals. >>> + >>> +Required Properties: >>> + >>> +- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" >>> +- compatible: CRU should be "rockchip,rk3399-cru" >>> +- reg: physical base address of the controller and length of memory >> mapped >> >>> + region. >>> +- #clock-cells: should be 1. >>> +- #reset-cells: should be 1. >>> + >>> +Optional Properties: >>> + >>> +- rockchip,grf: phandle to the syscon managing the "general register >> files" >> >>> + If missing, pll rates are not changeable, due to the missing pll lock >>> status. + >> the rk3399 doesn't need the GRF, so we should drop this block for now > actually, I just saw that the GRF is needed for the static settings during > init. So the rockchip,grf should stay but also move up to required > properties? > > Same for the grf-comment in the examples-section. > > I check the setting of the pclk_alive and pclk_pmu_src are not gating default on the PMUGRF_SOC_CON0, so I think that we don't need to do the static settings to re-enable them in the clock driver any more. Thanks. -- - Xing Zheng