From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751943AbcDIFZT (ORCPT ); Sat, 9 Apr 2016 01:25:19 -0400 Received: from avon.wwwdotorg.org ([70.85.31.133]:59802 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750899AbcDIFZR (ORCPT ); Sat, 9 Apr 2016 01:25:17 -0400 Subject: Re: [PATCH 4/4] irqchip: bcm2836: Use a more generic memory barrier call To: Eric Anholt References: <1459827858-3871-1-git-send-email-eric@anholt.net> <1459827858-3871-5-git-send-email-eric@anholt.net> <570497C7.10501@wwwdotorg.org> <87a8l40xox.fsf@eliezer.anholt.net> Cc: linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Lee Jones , Thomas Gleixner , Jason Cooper , Marc Zyngier From: Stephen Warren Message-ID: <5708927E.9030406@wwwdotorg.org> Date: Fri, 8 Apr 2016 23:26:22 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <87a8l40xox.fsf@eliezer.anholt.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/08/2016 12:20 PM, Eric Anholt wrote: > Stephen Warren writes: > >> On 04/04/2016 09:44 PM, Eric Anholt wrote: >>> dsb() requires an argument on arm64, so we needed to add "sy". >>> Instead, take this opportunity to switch to the same smp_wmb() call >>> that gic uses for its IPIs. This is a less strong barrier than we >>> were doing before (dmb(ishst) compared to dsb(sy)), but it seems to be >>> the correct one. >> >> I assume all MMIO is part of the ish domain? >> >> If so, the series, >> Acked-by: Stephen Warren > > I don't know if this barrier implies ordering all the way out to AXI on > this HW, but I don't think that's a requirement of this function. My understanding was that the barrier was explicitly to work around a bug in the bus fabric of the SoC, and hence the barrier very much does have to affect the transaction all the way out to AXI. Re-reading BCM2835-ARM-Peripherals.pdf section 1.3 "Peripheral access precautions for correct memory ordering" seems to confirm this.