From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754061AbcDJORr (ORCPT ); Sun, 10 Apr 2016 10:17:47 -0400 Received: from e28smtp01.in.ibm.com ([125.16.236.1]:36549 "EHLO e28smtp01.in.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753226AbcDJORq (ORCPT ); Sun, 10 Apr 2016 10:17:46 -0400 X-IBM-Helo: d28relay02.in.ibm.com X-IBM-MailFrom: xinhui@linux.vnet.ibm.com X-IBM-RcptTo: linux-kernel@vger.kernel.org Message-ID: <570A6078.2050002@linux.vnet.ibm.com> Date: Sun, 10 Apr 2016 22:17:28 +0800 From: Pan Xinhui User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.8.0 MIME-Version: 1.0 To: Peter Zijlstra CC: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Boqun Feng , Thomas Gleixner Subject: Re: [PATCH] powerpc: introduce {cmp}xchg for u8 and u16 References: <570752AA.9050603@linux.vnet.ibm.com> <20160408074744.GU3430@twins.programming.kicks-ass.net> In-Reply-To: <20160408074744.GU3430@twins.programming.kicks-ass.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-TM-AS-MML: disable x-cbid: 16041014-4790-0000-0000-00000EC3D110 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2016年04月08日 15:47, Peter Zijlstra wrote: > On Fri, Apr 08, 2016 at 02:41:46PM +0800, Pan Xinhui wrote: >> From: pan xinhui >> >> Implement xchg{u8,u16}{local,relaxed}, and >> cmpxchg{u8,u16}{,local,acquire,relaxed}. >> >> Atomic operation on 8-bit and 16-bit data type is supported from power7 > > And yes I see nothing P7 specific here, this implementation is for > everything PPC64 afaict, no? > Hello Peter, No, it's not for every ppc. So yes, I need add #ifdef here. Thanks for pointing it out. We might need a new config option and let it depend on POWER7/POWER8_CPU or even POWER9... > Also, note that you don't need explicit 8/16 bit atomics to implement > these. Its fine to use 32bit atomics and only modify half the word. > That is true. But I am a little worried about the performance. It will forbid any other tasks to touch the other half word during the load/reserve, right? I am working on the qspinlock implementation on PPC. Your and Waiman's patches are so nice. :) > Also, you might want to invest in some CPP to reduce the endless > repetition. > Will do that. thanks for your tips. thanks xinhui > Other than that, no objections :-) >