From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752530AbcDOQ2j (ORCPT ); Fri, 15 Apr 2016 12:28:39 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:3866 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751682AbcDOQ2h (ORCPT ); Fri, 15 Apr 2016 12:28:37 -0400 Subject: Re: [PATCH] arm64: dts: Add L2 cache topology to Hi6220 To: Leo Yan , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , "Catalin Marinas" , Will Deacon References: <1456464514-24380-1-git-send-email-leo.yan@linaro.org> CC: , , From: Wei Xu Message-ID: <5711149B.8000805@hisilicon.com> Date: Fri, 15 Apr 2016 17:19:39 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1456464514-24380-1-git-send-email-leo.yan@linaro.org> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.181.157] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.571114AC.02A1,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 2ce9a9fe9bee6c6d1349d17bb3bf64d2 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Leo, On 26/02/2016 05:28, Leo Yan wrote: > This patch adds the L2 cache topology on Hi6220. Hi6220 has two > clusters, every cluster has 512KiB L2 cache (32KiB x 16 ways). > > Signed-off-by: Leo Yan > --- Applied. Thanks! Best Regards, Wei > arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > index d8b963c..1746d50 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi > @@ -82,6 +82,7 @@ > device_type = "cpu"; > reg = <0x0 0x0>; > enable-method = "psci"; > + next-level-cache = <&CLUSTER0_L2>; > clocks = <&stub_clock 0>; > operating-points-v2 = <&cpu_opp_table>; > cooling-min-level = <4>; > @@ -96,6 +97,7 @@ > device_type = "cpu"; > reg = <0x0 0x1>; > enable-method = "psci"; > + next-level-cache = <&CLUSTER0_L2>; > operating-points-v2 = <&cpu_opp_table>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > }; > @@ -105,6 +107,7 @@ > device_type = "cpu"; > reg = <0x0 0x2>; > enable-method = "psci"; > + next-level-cache = <&CLUSTER0_L2>; > operating-points-v2 = <&cpu_opp_table>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > }; > @@ -114,6 +117,7 @@ > device_type = "cpu"; > reg = <0x0 0x3>; > enable-method = "psci"; > + next-level-cache = <&CLUSTER0_L2>; > operating-points-v2 = <&cpu_opp_table>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > }; > @@ -123,6 +127,7 @@ > device_type = "cpu"; > reg = <0x0 0x100>; > enable-method = "psci"; > + next-level-cache = <&CLUSTER1_L2>; > operating-points-v2 = <&cpu_opp_table>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > }; > @@ -132,6 +137,7 @@ > device_type = "cpu"; > reg = <0x0 0x101>; > enable-method = "psci"; > + next-level-cache = <&CLUSTER1_L2>; > operating-points-v2 = <&cpu_opp_table>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > }; > @@ -141,6 +147,7 @@ > device_type = "cpu"; > reg = <0x0 0x102>; > enable-method = "psci"; > + next-level-cache = <&CLUSTER1_L2>; > operating-points-v2 = <&cpu_opp_table>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > }; > @@ -150,9 +157,18 @@ > device_type = "cpu"; > reg = <0x0 0x103>; > enable-method = "psci"; > + next-level-cache = <&CLUSTER1_L2>; > operating-points-v2 = <&cpu_opp_table>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; > }; > + > + CLUSTER0_L2: l2-cache0 { > + compatible = "cache"; > + }; > + > + CLUSTER1_L2: l2-cache1 { > + compatible = "cache"; > + }; > }; > > cpu_opp_table: cpu_opp_table { >