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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b723f6e26d1sm248514466b.35.2025.11.04.08.43.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Nov 2025 08:43:07 -0800 (PST) Message-ID: <571d5733-be1b-449c-ba5a-414e0f950463@oss.qualcomm.com> Date: Tue, 4 Nov 2025 17:43:05 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PCI: qcom: Program correct T_POWER_ON value for L1.2 exit timing To: Krishna Chaitanya Chundru , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com References: <20251104-t_power_on_fux-v1-1-eb5916e47fd7@oss.qualcomm.com> <29b32098-39ca-440d-9b51-915157b752b5@oss.qualcomm.com> <2d4a192f-45b2-4aee-bcc9-dbe0dce0aa93@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <2d4a192f-45b2-4aee-bcc9-dbe0dce0aa93@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: D0gWKAnIdzobn9gWAm7TDxMZdqRL0Zh_ X-Proofpoint-GUID: D0gWKAnIdzobn9gWAm7TDxMZdqRL0Zh_ X-Authority-Analysis: v=2.4 cv=b7O/I9Gx c=1 sm=1 tr=0 ts=690a2d1c cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gdQQi2AoJGqifGrzje8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA0MDE0MCBTYWx0ZWRfX7Wp7QJHJY7bV k9PFBiu4IhR2MiFHs/yN4zrd40muJqVR8P2oWpynhMEjOBncrYlUrJz5BpKzAlJEeuvCRcM/aXY 5rwWfS66fni/0ZdrYeHz7gLtm0T6azgRufACgczUom0Lmp+JwmxpJX28t3qLl14M7JI41Bde1JG 4jgEwqVmLCRojTgSV78q+FGoY6a9HLR6qz4FqtDwqsEjiy3V91wJGnM1dZwwuAGXwMuGa2wBVyv MQ+9VtReOJEbJ4WM5ydPIUglESB6Am76MlXiElesLP5msHnOfXzeLk8eCGpHunSpOy1a9AS2XXA E0gtYWS1+50IsyhTLc6VyXOzhJ1xIVpxAJWhers/epGf68d+HSNq4A+phnVQ0o+JWCQuErXA7lW m+qkpfkDkVOQ8u75CanZr9V0SaWbiA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-04_02,2025-11-03_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511040140 On 11/4/25 5:38 PM, Krishna Chaitanya Chundru wrote: > > On 11/4/2025 5:59 PM, Konrad Dybcio wrote: >> On 11/4/25 1:12 PM, Krishna Chaitanya Chundru wrote: >>> The T_POWER_ON indicates the time (in μs) that a Port requires the port >>> on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# >>> asserted before actively driving the interface. This value is used by >>> the ASPM driver to compute the LTR_L1.2_THRESHOLD. >>> >>> Currently, the root port exposes a T_POWER_ON value of zero in the L1SS >>> capability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations. >>> This can result in improper L1.2 exit behavior and can trigger AER's. >>> >>> To address this, program the T_POWER_ON value to 80us (scale = 1, >>> value = 8) in the PCI_L1SS_CAP register during host initialization. This >>> ensures that ASPM can take the root port's T_POWER_ON value into account >>> while calculating the LTR_L1.2_THRESHOLD value. >> Is 80us a meaningful value, or "just happens to work"? > > This value is given by hardware team. Sorry I asked the wrong question Is it something that comes from the spec (PCI or DWC), or is it qc specific? Konrad