From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754848AbcEBSMQ (ORCPT ); Mon, 2 May 2016 14:12:16 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:2928 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754672AbcEBSMH (ORCPT ); Mon, 2 May 2016 14:12:07 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 02 May 2016 11:11:08 -0700 Message-ID: <5727959D.2020005@nvidia.com> Date: Mon, 2 May 2016 23:29:57 +0530 From: Laxman Dewangan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Rhyland Klein , , , CC: , , , Subject: Re: [PATCH 1/1] pinctrl: tegra: avoid parked_reg and parked_bank References: <1462199330-1536-1-git-send-email-ldewangan@nvidia.com> <57276D4E.2020204@nvidia.com> In-Reply-To: <57276D4E.2020204@nvidia.com> X-Originating-IP: [10.19.65.30] X-ClientProxiedBy: DRHKMAIL102.nvidia.com (10.25.59.16) To bgmail102.nvidia.com (10.25.59.11) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Monday 02 May 2016 08:37 PM, Rhyland Klein wrote: > On 5/2/2016 10:28 AM, Laxman Dewangan wrote: >> NVIDIA's Tegra210 support the park bit to make pinmux configuration >> enable/disable. If parked bit is 1 then configuration does not apply >> and if it is 0 then pinmux configuration applies. This is to support >> to avoid any glitch in pinmux configurations. >> >> The parked bit is part of mux register and mux bank and hence it is >> not required to have member for the parked_reg and parked bank very >> similar to other bit field of the same register. >> >> Remove the need of the parked register and parked bank and get whether >> parked function supported or not by parked_bit. >> >> This is to make the parked bit handling same as other fields of mux >> registers. >> >> Signed-off-by: Laxman Dewangan >> --- >> drivers/pinctrl/tegra/pinctrl-tegra.c | 8 ++++---- >> drivers/pinctrl/tegra/pinctrl-tegra.h | 6 +----- >> drivers/pinctrl/tegra/pinctrl-tegra114.c | 4 ++-- >> drivers/pinctrl/tegra/pinctrl-tegra124.c | 4 ++-- >> drivers/pinctrl/tegra/pinctrl-tegra20.c | 4 ++-- >> drivers/pinctrl/tegra/pinctrl-tegra210.c | 4 +--- >> drivers/pinctrl/tegra/pinctrl-tegra30.c | 4 ++-- >> 7 files changed, 14 insertions(+), 20 deletions(-) >> > These drivers are generated (with the exception of Tegra20) by the > tegra-pinmux-scripts hosted at : > https://github.com/NVIDIA/tegra-pinmux-scripts.git. Did you generate a > patch there so that the changes to pinctrl-tegra[114|124|210|30].c are > consistent there? If not you probably should. No, this is manual editing. Let me create patch on script to generate pinctrl-tegra[114|124|210|30].c as what this patch created manually.