From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934125AbcECQHb (ORCPT ); Tue, 3 May 2016 12:07:31 -0400 Received: from avon.wwwdotorg.org ([70.85.31.133]:45562 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932884AbcECQHX (ORCPT ); Tue, 3 May 2016 12:07:23 -0400 Subject: Re: [PATCH V2] pinctrl: tegra: avoid parked_reg and parked_bank To: Laxman Dewangan References: <1462214852-26915-1-git-send-email-ldewangan@nvidia.com> Cc: linus.walleij@linaro.org, thierry.reding@gmail.com, gnurou@gmail.com, rklein@nvidia.com, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org From: Stephen Warren Message-ID: <5728CCB9.9030209@wwwdotorg.org> Date: Tue, 3 May 2016 10:07:21 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1462214852-26915-1-git-send-email-ldewangan@nvidia.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/02/2016 12:47 PM, Laxman Dewangan wrote: > NVIDIA's Tegra210 support the park bit to make pinmux configuration > enable/disable. If parked bit is 1 then configuration does not apply > and if it is 0 then pinmux configuration applies. This is to support > to avoid any glitch in pinmux configurations. > > The parked bit is part of mux register and mux bank and hence it is > not required to have member for the parked_reg and parked bank very > similar to other bit field of the same register. > > Remove the need of the parked register and parked bank and get whether > parked function supported or not by parked_bit. > > This is to make the parked bit handling same as other fields of mux > registers. Acked-by: Stephen Warren