From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754749AbcEDR0C (ORCPT ); Wed, 4 May 2016 13:26:02 -0400 Received: from foss.arm.com ([217.140.101.70]:46710 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753355AbcEDR0A (ORCPT ); Wed, 4 May 2016 13:26:00 -0400 Subject: Re: [PATCH 2/2] irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratum To: Ray Jui , Thomas Gleixner , Jason Cooper References: <1462319245-32532-1-git-send-email-ray.jui@broadcom.com> <1462319245-32532-3-git-send-email-ray.jui@broadcom.com> <5729A9A3.6070207@arm.com> <964ae899-2fd1-baa4-521d-a31326281aa0@broadcom.com> Cc: linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, Alex Barba From: Marc Zyngier X-Enigmail-Draft-Status: N1110 Organization: ARM Ltd Message-ID: <572A30A4.2060806@arm.com> Date: Wed, 4 May 2016 18:25:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.7.0 MIME-Version: 1.0 In-Reply-To: <964ae899-2fd1-baa4-521d-a31326281aa0@broadcom.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Ray, On 04/05/16 17:20, Ray Jui wrote: > Hi Marc, > > On 5/4/2016 12:49 AM, Marc Zyngier wrote: >> On 04/05/16 00:47, Ray Jui wrote: >>> Alex Barba discovered Broadcom NS2 GICv2m >>> implementation has an erratum where the MSI data needs to be the SPI >>> number subtracted by an offset of 32, for the correct MSI interrupt to >>> be triggered. >>> >>> We are aware that APM X-Gene GICv2m has a similar erratum where the >>> MSI data needs to be the offset from the spi_start. While APM's workaround >>> is triggered based on readings from the MSI_IIDR register, this patch >>> contains a more general solution by allowing this offset to be >>> specified with an optional DT property 'arm,msi-offset-spi'. This patch >>> also maintains compatibility with existing APM platforms >> >> It may be more generic, but it also fails to deal with less capable >> firmware implementations. In contrast, reading MSI_IIDR is always >> possible (assuming you have a unique ID for this v2m implementation). >> >> If you cannot uniquely identify it using an ID register, the usual >> alternative is to have a new "compatible" string identifying the >> defective part, and set the offset based on this string. This still >> fails the ACPI test, but is the least invasive DT-wise. > > Okay. We do seem to have an ID. The JEP code looks a bit weird as the > IIDR register reads 0x13f. We were just a bit concerned that there's Ah, people get creative sometimes... > another chip from Broadcom that may happen to have the same ID but may > already have this offset issue fixed (or made worse with a different > offset, :) ). Since that chip has not even taped out yet, we can wait > till later to confirm. If a compatible string is needed in the future, > we'll add that. OK. It'd be good to make sure that this ID register is changed. I don't mind handling a different ID for the same quirk, but being unable to distinguish a quirky part from a fixed one would be pretty dumb. > For now, I'm going to submit another patch to deal with this offset > based on IIDR reading 0x13f. Sounds good. Thanks, M. -- Jazz is not dead. It just smells funny...