From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753506AbcEEMnp (ORCPT ); Thu, 5 May 2016 08:43:45 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:7946 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750905AbcEEMno (ORCPT ); Thu, 5 May 2016 08:43:44 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 05 May 2016 05:43:03 -0700 Subject: Re: [PATCH V3 2/4] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl() To: Laxman Dewangan , , , References: <1462361973-27990-1-git-send-email-ldewangan@nvidia.com> <1462361973-27990-3-git-send-email-ldewangan@nvidia.com> <572B173D.6030108@nvidia.com> <572B17DA.901@nvidia.com> CC: , , , From: Jon Hunter Message-ID: <572B3FF9.8080202@nvidia.com> Date: Thu, 5 May 2016 13:43:37 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <572B17DA.901@nvidia.com> X-Originating-IP: [10.21.132.133] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/05/16 10:52, Laxman Dewangan wrote: > > On Thursday 05 May 2016 03:19 PM, Jon Hunter wrote: >> On 04/05/16 12:39, Laxman Dewangan wrote: >>> The function tegra_pmc_readl() returns the u32 type data and hence >>> change the data type of variable where this data is stored to u32 >>> type. >>> >>> Signed-off-by: Laxman Dewangan >>> >>> --- >>> Changes from V1: >>> -This is new in series as per discussion on V1 series to use u32 for >>> tegra_pmc_readl. >>> >>> Changes from V2: >>> - Make unsigned long to u32 for some missed variable from V1. >>> --- >>> drivers/soc/tegra/pmc.c | 24 ++++++++++++++---------- >>> 1 file changed, 14 insertions(+), 10 deletions(-) >>> >>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c >>> index 2c3f1f9..eff9425 100644 >>> --- a/drivers/soc/tegra/pmc.c >>> +++ b/drivers/soc/tegra/pmc.c >>> @@ -844,7 +844,8 @@ static void tegra_powergate_init(struct tegra_pmc >>> *pmc) >>> static int tegra_io_rail_prepare(unsigned int id, unsigned long >>> *request, >>> unsigned long *status, unsigned int *bit) >>> { >>> - unsigned long rate, value; >>> + unsigned long rate; >>> + u32 value; >>> *bit = id % 32; >>> @@ -868,17 +869,18 @@ static int tegra_io_rail_prepare(unsigned int >>> id, unsigned long *request, >>> tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); >>> /* must be at least 200 ns, in APB (PCLK) clock cycles */ >>> - value = DIV_ROUND_UP(1000000000, rate); >>> - value = DIV_ROUND_UP(200, value); >>> + rate = DIV_ROUND_UP(1000000000, rate); >>> + rate = DIV_ROUND_UP(200, rate); >>> + value = (u32)rate; >> Although it is unlikely, I think that we should check it is less >> than U32_MAX, return an error if it is not. > > rate = DIV_ROUNC_UP(200, rate) means > > rate = (200 + rate -1)/rate > > and can not be more than 200 in any case (if rate =1). > So no need of the error check. OK, yes you are right. In that case there is no need to cast and so I would leave this code as-is and not change the type. Jon