From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752001AbcEJRrz (ORCPT ); Tue, 10 May 2016 13:47:55 -0400 Received: from mail-pa0-f43.google.com ([209.85.220.43]:34836 "EHLO mail-pa0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751930AbcEJRrx (ORCPT ); Tue, 10 May 2016 13:47:53 -0400 Subject: Re: [PATCH 00/12] TLB/XPA fixes & cleanups To: Ralf Baechle , Paul Burton References: <1460716620-13382-1-git-send-email-paul.burton@imgtec.com> <20160510124426.GG16402@linux-mips.org> Cc: linux-mips@linux-mips.org, James Hogan , Adam Buchbinder , "Maciej W. Rozycki" , Joshua Kinard , Huacai Chen , "Maciej W. Rozycki" , Paul Gortmaker , "Aneesh Kumar K.V" , linux-kernel@vger.kernel.org, "Peter Zijlstra (Intel)" , David Hildenbrand , Andrew Morton , David Daney , Jonas Gorski , Markos Chandras , Ingo Molnar , Alex Smith , "Kirill A. Shutemov" From: Florian Fainelli Message-ID: <57321EC4.5030301@gmail.com> Date: Tue, 10 May 2016 10:47:48 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <20160510124426.GG16402@linux-mips.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/10/2016 05:44 AM, Ralf Baechle wrote: > On Fri, Apr 15, 2016 at 11:36:48AM +0100, Paul Burton wrote: > >> This series fixes up a number of issues introduced by commit >> c5b367835cfc ("MIPS: Add support for XPA."), including breakage of the >> MIPS32 with 36 bit physical addressing case & clobbering of $1 upon TLB >> refill exceptions. Along the way a number of cleanups are made, which >> leaves pgtable-bits.h in particular much more readable than before. >> >> The series applies atop v4.6-rc3. >> >> James Hogan (4): >> MIPS: Separate XPA CPU feature into LPA and MVH >> MIPS: Fix HTW config on XPA kernel without LPA enabled >> MIPS: mm: Don't clobber $1 on XPA TLB refill >> MIPS: mm: Don't do MTHC0 if XPA not present >> >> Paul Burton (8): >> MIPS: Remove redundant asm/pgtable-bits.h inclusions >> MIPS: Use enums to make asm/pgtable-bits.h readable >> MIPS: mm: Standardise on _PAGE_NO_READ, drop _PAGE_READ >> MIPS: mm: Unify pte_page definition >> MIPS: mm: Fix MIPS32 36b physical addressing (alchemy, netlogic) >> MIPS: mm: Pass scratch register through to iPTE_SW >> MIPS: mm: Be more explicit about PTE mode bit handling >> MIPS: mm: Simplify build_update_entries > > Applied - but "MIPS: Separate XPA CPU feature into LPA and MVH" causes > a massive conflict with Florian's RIXI patches > > [3/6] MIPS: Allow RIXI to be used on non-R2 or R6 core > [4/6] MIPS: Move RIXI exception enabling after vendor-specific cpu_probe > [5/6] MIPS: BMIPS: BMIPS4380 and BMIPS5000 support RIXI > > I figured unapplying those three, applying Paul's series then re-applying > Florian's patch on top of the whole series will be the easier path as in > leaving me with the smaller rejects to manage. Did you already push that to mips-for-linux-next? I can give it a quick spin once you do so. -- Florian