From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932434AbcEKPff (ORCPT ); Wed, 11 May 2016 11:35:35 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:14651 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751460AbcEKPfd (ORCPT ); Wed, 11 May 2016 11:35:33 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 11 May 2016 08:34:39 -0700 Subject: Re: [PATCH V4 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage To: Laxman Dewangan , , , , References: <1462531548-12914-1-git-send-email-ldewangan@nvidia.com> <1462531548-12914-4-git-send-email-ldewangan@nvidia.com> <572CAC20.9030307@nvidia.com> <572CB906.3090004@nvidia.com> <572F2D84.3060505@nvidia.com> <57333366.2040500@nvidia.com> CC: , , From: Jon Hunter X-Nvconfidentiality: public Message-ID: <5733513E.9080606@nvidia.com> Date: Wed, 11 May 2016 16:35:26 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <57333366.2040500@nvidia.com> X-Originating-IP: [10.21.132.102] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/05/16 14:28, Laxman Dewangan wrote: > On Sunday 08 May 2016 05:43 PM, Jon Hunter wrote: >> On 06/05/16 16:32, Laxman Dewangan wrote: >>> On Friday 06 May 2016 08:07 PM, Jon Hunter wrote: >>>> On 06/05/16 11:45, Laxman Dewangan wrote: >>>> + >>>> + /* Last entry */ >>>> + TEGRA_IO_PAD_MAX, >>>> Nit should these be TEGRA_IO_PADS_xxx? >>> Because this was name of single pad and hence I said TEGRA_IO_PAD_XXX. >> Aren't these used to set the voltage level and power state for the >> entire group of IOs? Confused :-( > > One IO pad can have multiple IO pins. > IO Pad control the power state and voltage of all pins belongs to that > IO pad. Ugh ... I remember for xusb there was something similar we the Tegra docs used pad to imply multiple. However, in general pad == pin == ball or at least should. > Now what should we say PADS or PAD here? TEGRA_IO_PAD_UART or > TEGRA_IO_PADS_UART? Personally, I think pads and that is purely because it aligns with the APIs. I think that the APIs names, tegra_io_pads_xxx() should be consistent with the enum naming. >>>>> +}; >>>>> + >>>>> +/* tegra_io_pads_source_voltage: The voltage level of IO rails which >>>>> source >>>>> + * the IO pads. >>>>> + */ >>>>> +enum tegra_io_pads_source_voltage { >>>>> + TEGRA_IO_PADS_SOURCE_VOLTAGE_1800000UV, >>>>> + TEGRA_IO_PADS_SOURCE_VOLTAGE_3300000UV, >>>>> +}; >>>> Nit I wonder if we can make this shorter ... >>>> >>>> enum tegra_io_pads_vconf { >>>> TEGRA_IO_PADS_VCONF_1V8, >>>> TEGRA_IO_PADS_VCONF_3V3, >>> This looks good but for voltage and current, unit is used uV/uV across >>> the system. So wanted to have same unit. >> Now it is an enum does it matter? Or maybe just have ... >> >> enum tegra_io_pads_vconf { >> TEGRA_IO_PADS_1800000UV, >> TEGRA_IO_PADS_3300000UV, >> }; >> > > OK, TEGRA_IO_PADS_VCONF_1800000UV and TEGRA_IO_PADS_VCONF_3300000UV. > Fine? Fine :-) Jon