From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751901AbcELBIr (ORCPT ); Wed, 11 May 2016 21:08:47 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:43112 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751497AbcELBIp (ORCPT ); Wed, 11 May 2016 21:08:45 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <9d810afe50c0410818b5951286fabc12> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v8 7/8] i2c: rk3x: add i2c support for rk3399 soc To: Doug Anderson References: <1462908252-27016-1-git-send-email-david.wu@rock-chips.com> <1462908698-27284-1-git-send-email-david.wu@rock-chips.com> Cc: =?UTF-8?Q?Heiko_St=c3=bcbner?= , Wolfram Sang , Rob Herring , Andy Shevchenko , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Brian Norris , David Riley , Tao Huang , Lin Huang , Jianqun Xu , Chris , Eddie Cai , "linux-arm-kernel@lists.infradead.org" , "open list:ARM/Rockchip SoC..." , "linux-i2c@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" From: "David.Wu" Message-ID: <5733D7AA.1060500@rock-chips.com> Date: Thu, 12 May 2016 09:08:58 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Doug, 在 2016/5/12 1:37, Doug Anderson 写道: > Hi, > > On Tue, May 10, 2016 at 12:31 PM, David Wu wrote: >> static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate) >> { >> struct i2c_timings *t = &i2c->t; >> struct rk3x_i2c_calced_timings calc; >> u64 t_low_ns, t_high_ns; >> + u32 val; >> int ret; >> >> - ret = rk3x_i2c_calc_divs(clk_rate, t, &calc); >> + ret = i2c->soc_data->calc_timings(clk_rate, t, &calc); >> WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz); >> >> - clk_enable(i2c->clk); >> + clk_enable(i2c->pclk); >> + >> i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff), >> REG_CLKDIV); >> - clk_disable(i2c->clk); >> + >> + val = i2c_readl(i2c, REG_CON); >> + val &= ~REG_CON_TUNING_MASK; >> + val |= calc.tuning; >> + i2c_writel(i2c, val, REG_CON); > > Another subtle bug here. You need to be holding the spinlock here > since you're doing a read-modify-write of a register that is also > touched by the interrupt handler. We never needed it before because > the previous register update wasn't touched by anyone else and it was > a single atomic write. > > Also: technically if we are midway through a transfer when all this > happens then there will be a very short period of time when the two > timing-related registers won't match with each other. I have no idea > how much that would matter, but in the very least it seems wise to > minimize the time where they mismatch. So I'd probably write: > > spin_lock_irqsave(&i2c->lock, flags); > val = i2c_readl(i2c, REG_CON); > val &= ~REG_CON_TUNING_MASK; > val |= calc.tuning; > i2c_writel(i2c, val, REG_CON); > i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff), > REG_CLKDIV); > spin_unlock_irqrestore(&i2c->lock, flags); > > ...if we really end up with on a system with a dynamically changing > clock that uses the new-style timing and we see real problems, we can > always try to come up with a way to avoid any problems. Sound OK? > > Good, add spin_lock is very necessary for atomic write here, thanks for your advice. > Otherwise, I think things look good to me. Caesar's comments would > also be good to fix. > > > -Doug > > >