From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752589AbcERGzD (ORCPT ); Wed, 18 May 2016 02:55:03 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:50741 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751918AbcERGyM (ORCPT ); Wed, 18 May 2016 02:54:12 -0400 Subject: Re: [PATCH 3/3] irqchip: mips-gic: Setup EIC mode on each CPU if it's in use To: Paul Burton , , "Ralf Baechle" References: <1463495466-29689-1-git-send-email-paul.burton@imgtec.com> <1463495466-29689-4-git-send-email-paul.burton@imgtec.com> CC: Marc Zyngier , Jason Cooper , Thomas Gleixner , From: Matt Redfearn Message-ID: <573C1191.80707@imgtec.com> Date: Wed, 18 May 2016 07:54:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1463495466-29689-4-git-send-email-paul.burton@imgtec.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [192.168.154.116] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/05/16 15:31, Paul Burton wrote: > When EIC mode is in use (cpu_has_veic is true) enable it on each CPU > during GIC initialisation. Otherwise there may be a mismatch between the > hardware default interrupt model & that expected by the kernel. > > Signed-off-by: Paul Burton > --- > > drivers/irqchip/irq-mips-gic.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c > index 4dffccf..bc23c92 100644 > --- a/drivers/irqchip/irq-mips-gic.c > +++ b/drivers/irqchip/irq-mips-gic.c > @@ -956,7 +956,7 @@ static void __init __gic_init(unsigned long gic_base_addr, > unsigned int cpu_vec, unsigned int irqbase, > struct device_node *node) > { > - unsigned int gicconfig; > + unsigned int gicconfig, cpu; > unsigned int v[2]; > > __gic_base_addr = gic_base_addr; > @@ -973,6 +973,14 @@ static void __init __gic_init(unsigned long gic_base_addr, > gic_vpes = gic_vpes + 1; > > if (cpu_has_veic) { > + /* Set EIC mode for all VPEs */ > + for_each_present_cpu(cpu) { > + gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), > + mips_cm_vp_id(cpu)); > + gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL), > + GIC_VPE_CTL_EIC_MODE_MSK); > + } > + > /* Always use vector 1 in EIC mode */ > gic_cpu_pin = 0; > timer_cpu_pin = gic_cpu_pin; Hi Paul Reviewed-by: Matt Redfearn Tested-by: Matt Redfearn Thanks, Matt