[PATCH 1/2] MIPS: Add definitions of SegCtl registers and use them

[PATCH 1/2] MIPS: Add definitions of SegCtl registers and use them

[Matt Redfearn]

The SegCtl registers are standard for MIPSr3..MIPSr5. Add definitions of
these registers and use them rather than constants

Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
---

 arch/mips/include/asm/mach-malta/kernel-entry-init.h | 6 +++---
 arch/mips/include/asm/mipsregs.h                     | 3 +++
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/mips/include/asm/mach-malta/kernel-entry-init.h b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
index 0cf8622db27f..ab03eb3fadac 100644
--- a/arch/mips/include/asm/mach-malta/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-malta/kernel-entry-init.h
@@ -56,7 +56,7 @@
 		(0 << MIPS_SEGCFG_PA_SHIFT) |				\
 		(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
 	or	t0, t2
-	mtc0	t0, $5, 2
+	mtc0	t0, CP0_SEGCTL0
 
 	/* SegCtl1 */
 	li      t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |	\
@@ -67,7 +67,7 @@
 		(0 << MIPS_SEGCFG_PA_SHIFT) |				\
 		(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
 	ins	t0, t1, 16, 3
-	mtc0	t0, $5, 3
+	mtc0	t0, CP0_SEGCTL1
 
 	/* SegCtl2 */
 	li	t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |	\
@@ -77,7 +77,7 @@
 		(4 << MIPS_SEGCFG_PA_SHIFT) |				\
 		(1 << MIPS_SEGCFG_EU_SHIFT)) << 16)
 	or	t0, t2
-	mtc0	t0, $5, 4
+	mtc0	t0, CP0_SEGCTL2
 
 	jal	mips_ihb
 	mfc0    t0, $16, 5
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 3ad19ad04d8a..639137f12f1a 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -48,6 +48,9 @@
 #define CP0_CONF $3
 #define CP0_CONTEXT $4
 #define CP0_PAGEMASK $5
+#define CP0_SEGCTL0 $5, 2
+#define CP0_SEGCTL1 $5, 3
+#define CP0_SEGCTL2 $5, 4
 #define CP0_WIRED $6
 #define CP0_INFO $7
 #define CP0_HWRENA $7, 0
-- 
2.5.0

[PATCH 2/2] MIPS: CPS: Copy EVA configuration when starting secondary VPs.

[Matt Redfearn]

When starting secondary VPEs which support EVA and the SegCtl registers,
copy the memory segmentation configuration from the running VPE to ensure
that all VPEs in the core have a consitent virtual memory map.

The EVA configuration of secondary cores is dealt with when starting the
core via the CM.

Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
---

 arch/mips/kernel/cps-vec.S | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index ac81edd44563..07b3274c8ae1 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -431,6 +431,22 @@ LEAF(mips_cps_boot_vpes)
 	mfc0	t0, CP0_CONFIG
 	mttc0	t0, CP0_CONFIG
 
+	/* Copy the EVA config from this VPE if the CPU supports it */
+	mfc0	t0, CP0_CONFIG, 1
+	bgez	t0, 1f
+	 mfc0	t0, CP0_CONFIG, 2
+	bgez	t0, 1f
+	 mfc0	t0, CP0_CONFIG, 3
+	and	t0, t0, MIPS_CONF3_SC
+	beqz	t0, 1f
+	 nop
+	mfc0    t0, CP0_SEGCTL0
+	mttc0	t0, CP0_SEGCTL0
+	mfc0    t0, CP0_SEGCTL1
+	mttc0	t0, CP0_SEGCTL1
+	mfc0    t0, CP0_SEGCTL2
+	mttc0	t0, CP0_SEGCTL2
+1:
 	/* Ensure no software interrupts are pending */
 	mttc0	zero, CP0_CAUSE
 	mttc0	zero, CP0_STATUS
-- 
2.5.0

Re: [PATCH 2/2] MIPS: CPS: Copy EVA configuration when starting secondary VPs.

[Paul Burton]

On Wed, May 18, 2016 at 03:45:22PM +0100, Matt Redfearn wrote:
> When starting secondary VPEs which support EVA and the SegCtl registers,
> copy the memory segmentation configuration from the running VPE to ensure
> that all VPEs in the core have a consitent virtual memory map.
> 
> The EVA configuration of secondary cores is dealt with when starting the
> core via the CM.
> 
> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
> ---
> 
>  arch/mips/kernel/cps-vec.S | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
> index ac81edd44563..07b3274c8ae1 100644
> --- a/arch/mips/kernel/cps-vec.S
> +++ b/arch/mips/kernel/cps-vec.S
> @@ -431,6 +431,22 @@ LEAF(mips_cps_boot_vpes)
>  	mfc0	t0, CP0_CONFIG
>  	mttc0	t0, CP0_CONFIG
>  
> +	/* Copy the EVA config from this VPE if the CPU supports it */
> +	mfc0	t0, CP0_CONFIG, 1
> +	bgez	t0, 1f
> +	 mfc0	t0, CP0_CONFIG, 2
> +	bgez	t0, 1f
> +	 mfc0	t0, CP0_CONFIG, 3
> +	and	t0, t0, MIPS_CONF3_SC
> +	beqz	t0, 1f
> +	 nop

Hi Matt,

The checks here aren't *quite* right since they do the mfc0 of the next
register in the delay slot which will happen even if the M bit of the
preceeding register wasn't set. There are other cases in cps-vec.S where
I've made that mistake... Luckily, in this particular case, we know that
we have MT ASE support which means we know that Config3 exists. So I
think you can just remove the checks of Config1.M & Config2.M and just
read Config3 straight away.

Thanks,
    Paul

> +	mfc0    t0, CP0_SEGCTL0
> +	mttc0	t0, CP0_SEGCTL0
> +	mfc0    t0, CP0_SEGCTL1
> +	mttc0	t0, CP0_SEGCTL1
> +	mfc0    t0, CP0_SEGCTL2
> +	mttc0	t0, CP0_SEGCTL2
> +1:
>  	/* Ensure no software interrupts are pending */
>  	mttc0	zero, CP0_CAUSE
>  	mttc0	zero, CP0_STATUS
> -- 
> 2.5.0
> 

Re: [PATCH 2/2] MIPS: CPS: Copy EVA configuration when starting secondary VPs.

[Matt Redfearn]

On 18/05/16 16:04, Paul Burton wrote:
> On Wed, May 18, 2016 at 03:45:22PM +0100, Matt Redfearn wrote:
>> When starting secondary VPEs which support EVA and the SegCtl registers,
>> copy the memory segmentation configuration from the running VPE to ensure
>> that all VPEs in the core have a consitent virtual memory map.
>>
>> The EVA configuration of secondary cores is dealt with when starting the
>> core via the CM.
>>
>> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
>> ---
>>
>>   arch/mips/kernel/cps-vec.S | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
>> index ac81edd44563..07b3274c8ae1 100644
>> --- a/arch/mips/kernel/cps-vec.S
>> +++ b/arch/mips/kernel/cps-vec.S
>> @@ -431,6 +431,22 @@ LEAF(mips_cps_boot_vpes)
>>   	mfc0	t0, CP0_CONFIG
>>   	mttc0	t0, CP0_CONFIG
>>   
>> +	/* Copy the EVA config from this VPE if the CPU supports it */
>> +	mfc0	t0, CP0_CONFIG, 1
>> +	bgez	t0, 1f
>> +	 mfc0	t0, CP0_CONFIG, 2
>> +	bgez	t0, 1f
>> +	 mfc0	t0, CP0_CONFIG, 3
>> +	and	t0, t0, MIPS_CONF3_SC
>> +	beqz	t0, 1f
>> +	 nop
> Hi Matt,
>
> The checks here aren't *quite* right since they do the mfc0 of the next
> register in the delay slot which will happen even if the M bit of the
> preceeding register wasn't set. There are other cases in cps-vec.S where
> I've made that mistake... Luckily, in this particular case, we know that
> we have MT ASE support which means we know that Config3 exists. So I
> think you can just remove the checks of Config1.M & Config2.M and just
> read Config3 straight away.
Good point - thanks Paul :-)

Matt
>
> Thanks,
>      Paul
>
>> +	mfc0    t0, CP0_SEGCTL0
>> +	mttc0	t0, CP0_SEGCTL0
>> +	mfc0    t0, CP0_SEGCTL1
>> +	mttc0	t0, CP0_SEGCTL1
>> +	mfc0    t0, CP0_SEGCTL2
>> +	mttc0	t0, CP0_SEGCTL2
>> +1:
>>   	/* Ensure no software interrupts are pending */
>>   	mttc0	zero, CP0_CAUSE
>>   	mttc0	zero, CP0_STATUS
>> -- 
>> 2.5.0
>>