Re: [PATCH v4 1/4] perf amd ibs: Add Load Latency bits in raw dump

[Ravi Bangoria <ravi.bangoria@amd.com>]

Hi Namhyung,

>> +	# perf record -e ibs_op/ldlat=128/ -c 100000 -a
>> +
>> +	Supported load latency threshold values are 128 to 2048 (both inclusive).
> 
> What happens if user gives an out of range value?

Kernel returns error.

>>  static void pr_ibs_op_ctl(union ibs_op_ctl reg)
>>  {
>>  	char l3_miss_only[sizeof(" L3MissOnly _")] = "";
>> +	char ldlat[sizeof(" LdLatThrsh __ LdLatEn _")] = "";
> 
> Shouldn't it reserve 4 characters for the threshold since it can be up
> to 2048?

This function dumps HW register content. IBS_OP_CTL[LdLatThrsh] is a
4 bit field which should be programmed as:

  (actual threshold / 128) - 1

Valid values for LdLatThrsh are 0 to 15.

>>  	if (zen4_ibs_extensions)
>>  		snprintf(l3_miss_only, sizeof(l3_miss_only), " L3MissOnly %d", reg.l3_miss_only);
>>  
>> -	printf("ibs_op_ctl:\t%016llx MaxCnt %9d%s En %d Val %d CntCtl %d=%s CurCnt %9d\n",
>> +	if (ldlat_cap) {
>> +		snprintf(ldlat, sizeof(ldlat), " LdLatThrsh %2d LdLatEn %d",
> 
> Here, it would be %4d.

Since the valid values for LdLatThrsh are 0 to 15, two characters are
sufficient.

Thanks,
Ravi