From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756141AbcEWNqW (ORCPT ); Mon, 23 May 2016 09:46:22 -0400 Received: from sessmg22.ericsson.net ([193.180.251.58]:63282 "EHLO sessmg22.ericsson.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756101AbcEWNqU (ORCPT ); Mon, 23 May 2016 09:46:20 -0400 X-AuditID: c1b4fb3a-f79386d00000467b-0c-574309a98924 Subject: [PATCH] microblaze: fix instruction cache invalidation To: CC: Michal Simek From: Romeo Cane Organization: Ericsson AB Message-ID: <574309A9.1000804@ericsson.com> Date: Mon, 23 May 2016 14:46:17 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPLMWRmVeSWpSXmKPExsUyM2K7pe4qTudwg/ntbBaXd81hs3jy8TSL A5PH364pzB6fN8kFMEVx2aSk5mSWpRbp2yVwZXz7FlTwXajiU+8j1gbGh/xdjJwcEgImEu+m HWWCsMUkLtxbz9bFyMUhJHCEUeLipo9Qziog5/9EsCphAXuJJ2tuMYPYIgJKEt+vdTOC2MwC yhLvdkxmBbHZBLQkrt/+zwJi8wtISmxo2A1WzyugLdHYswKohoODRUBV4vqvBJCwqECExKzt P5ggSgQlTs58wgJSwiygKbF+lz7EdHmJ7W/nMIOEhQRUJHYujJzAKDALScMshIZZSBoWMDKv YhQtTi0uzk03MtJLLcpMLi7Oz9PLSy3ZxAgMxoNbflvtYDz43PEQowAHoxIP7wNtp3Ah1sSy 4srcQ4wSHMxKIry/OZzDhXhTEiurUovy44tKc1KLDzFKc7AoifP6v1QMFxJITyxJzU5NLUgt gskycXBKNTDq1KduWugzge2uXVRMk88khZczQ8KnHFDZK15VGKU0+WLSkrnWE2YYNavt57P5 /sh0n5Oe6N0O09xF/+5Z3aq2CH+813zSGR27WK/J2XvVk76901jide/d13OJ0jLhT4x2fE/x /djm18Rx5Hho2Da9SxNUL4rp+Lj/c2mx2rc8dKF0EP81yddKLMUZiYZazEXFiQDLHssiQgIA AA== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Microblaze invalidates the instruction cache via WIC opcode which, unlike WDC for data cache, requires the virtual address of the target location when MMU is used. The current code always uses the physical address, preventing the instruction cache to be properly invalidated and exposing the risk of user space applications to crash with signal 4 (illegal instruction) when executing the trampoline code in return from a signal handler. Same issue when the code is modified via copy_to_user_page. This patch fixes the calls to instruction cache invalidation using the correct addresses. Signed-off-by: Romeo Cane --- arch/microblaze/include/asm/cacheflush.h | 6 +++--- arch/microblaze/kernel/signal.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h index ffea82a..c978e64 100644 --- a/arch/microblaze/include/asm/cacheflush.h +++ b/arch/microblaze/include/asm/cacheflush.h @@ -106,11 +106,11 @@ static inline void copy_to_user_page(struct vm_area_struct *vma, struct page *page, unsigned long vaddr, void *dst, void *src, int len) { - u32 addr = virt_to_phys(dst); + u32 paddr = virt_to_phys(dst); memcpy(dst, src, len); if (vma->vm_flags & VM_EXEC) { - invalidate_icache_range(addr, addr + PAGE_SIZE); - flush_dcache_range(addr, addr + PAGE_SIZE); + invalidate_icache_range(vaddr, vaddr + PAGE_SIZE); + flush_dcache_range(paddr, paddr + PAGE_SIZE); } } diff --git a/arch/microblaze/kernel/signal.c b/arch/microblaze/kernel/signal.c index 9700152..757dd40 100644 --- a/arch/microblaze/kernel/signal.c +++ b/arch/microblaze/kernel/signal.c @@ -200,6 +200,7 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, address), address); preempt_disable(); + invalidate_icache_range(address, address + 8); ptep = pte_offset_map(pmdp, address); if (pte_present(*ptep)) { address = (unsigned long) page_address(pte_page(*ptep)); @@ -207,7 +208,6 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, address += ((unsigned long)frame->tramp) & ~PAGE_MASK; /* MS address is virtual */ address = __virt_to_phys(address); - invalidate_icache_range(address, address + 8); flush_dcache_range(address, address + 8); } pte_unmap(ptep); -- 1.9.1