From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932457AbcEWOBz (ORCPT ); Mon, 23 May 2016 10:01:55 -0400 Received: from eusmtp01.atmel.com ([212.144.249.242]:12117 "EHLO eusmtp01.atmel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932440AbcEWOBx (ORCPT ); Mon, 23 May 2016 10:01:53 -0400 Subject: Re: [PATCH 1/2] mtd: spi-nor: disable software protection for Macronix flash at startup To: Matthias Schiffer , , References: From: Cyrille Pitchen CC: Felix Fietkau Message-ID: <57430D4C.3010000@atmel.com> Date: Mon, 23 May 2016 16:01:48 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.161.30.18] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Matthias, Le 18/05/2016 15:32, Matthias Schiffer a écrit : > This patch has been tested in OpenWrt for a few months and seems to work > correctly. > > Signed-off-by: Felix Fietkau > Signed-off-by: Matthias Schiffer > --- > drivers/mtd/spi-nor/spi-nor.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 157841d..d681003 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -1304,6 +1304,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) > > if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || > JEDEC_MFR(info) == SNOR_MFR_INTEL || > + JEDEC_MFR(info) == SNOR_MFR_MACRONIX || > JEDEC_MFR(info) == SNOR_MFR_SST || > info->flags & SPI_NOR_HAS_LOCK) { > write_enable(nor); > The line following this patch chunk is "write_sr(nor, 0);" however, if I refer to the Macronix mx25l25673g datasheet about the Status Register, bits[5:2] (BP0, BP1, BP2 and BP3) are non-volatile and define the protected area. Also bit6 (Quad Enable) is also non-volatile and is used to reassign #WP and #Hold pins to IO2 and IO3 functions needed by Quad SPI protocols on many other Macronix memories (indeed on the 73g part, the Quad Enable bit is always 1). So you should not write 0 directly into the Status Register if you only want to clear bit7 (Status Register Write Disable): use a read, modify, write sequence instead. Best regards, Cyrille