From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755385AbcEXKs7 (ORCPT ); Tue, 24 May 2016 06:48:59 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:7871 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755221AbcEXKs5 (ORCPT ); Tue, 24 May 2016 06:48:57 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 24 May 2016 03:47:24 -0700 Subject: Re: [PATCH V7 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage To: Laxman Dewangan , , , References: <1463755530-20941-1-git-send-email-ldewangan@nvidia.com> <1463755530-20941-4-git-send-email-ldewangan@nvidia.com> <5742C773.6080609@nvidia.com> CC: , , , From: Jon Hunter Message-ID: <57443193.5010900@nvidia.com> Date: Tue, 24 May 2016 11:48:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <5742C773.6080609@nvidia.com> X-Originating-IP: [10.21.132.103] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL102.nvidia.com (10.26.138.15) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/05/16 10:03, Jon Hunter wrote: > > On 20/05/16 15:45, Laxman Dewangan wrote: >> The IO pins of Tegra SoCs are grouped for common control of IO >> interface like setting voltage signal levels and power state of >> the interface. The group is generally referred as IO pads. The >> power state and voltage control of IO pins can be done at IO pads >> level. >> >> Tegra generation SoC supports the power down of IO pads when it >> is not used even in the active state of system. This saves power >> from that IO interface. Also it supports multiple voltage level >> in IO pins for interfacing on some of pads. The IO pad voltage is >> automatically detected till T124, hence SW need not to configure >> this. But from T210, the automatically detection logic has been >> removed, hence SW need to explicitly set the IO pad voltage into >> IO pad configuration registers. >> >> Add support to set the power states and voltage level of the IO pads >> from client driver. The implementation for the APIs are in generic >> which is applicable for all generation os Tegra SoC. >> >> IO pads ID and information of bit field for power state and voltage >> level controls are added for Tegra124, Tegra132 and Tegra210. The SOR >> driver is modified to use the new APIs. >> >> Signed-off-by: Laxman Dewangan > > Thanks. I will defer to Thierry on how this should be organised for > merging but I am happy with the code. There is one minor typo below, but > otherwise ... > > Acked-by: Jon Hunter I have tested this on a Tegra124 Nyan Big and verified that the SOR IO pads are turning on and off and no errors are seen. I have also boot tested this series on our upstream test farm and not seen any regressions. So ... Tested-by: Jon Hunter Cheers Jon