From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753096AbcEYHsz (ORCPT ); Wed, 25 May 2016 03:48:55 -0400 Received: from mailout3.w1.samsung.com ([210.118.77.13]:16469 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751015AbcEYHsw (ORCPT ); Wed, 25 May 2016 03:48:52 -0400 X-AuditID: cbfec7f5-f792a6d000001302-8d-574558e05887 Subject: Re: [PATCH 2/2] ARM: dts: Add async-bridge clock to MFC power domain for Exynos5420 To: Javier Martinez Canillas , linux-kernel@vger.kernel.org References: <1464111662-15336-1-git-send-email-javier@osg.samsung.com> <1464111662-15336-3-git-send-email-javier@osg.samsung.com> Cc: devicetree@vger.kernel.org, Kukjin Kim , Michael Turquette , Marek Szyprowski , Mauro Carvalho Chehab , Shuah Khan , Stephen Boyd , linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sylwester Nawrocki , Tomasz Figa , linux-clk@vger.kernel.org, Nicolas Dufresne From: Krzysztof Kozlowski X-Enigmail-Draft-Status: N1110 Message-id: <574558DF.1090000@samsung.com> Date: Wed, 25 May 2016 09:48:47 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-version: 1.0 In-reply-to: <1464111662-15336-3-git-send-email-javier@osg.samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKIsWRmVeSWpSXmKPExsVy+t/xy7oPIlzDDXauNbGYf+Qcq8Wbt2uY LF6/MLTof/ya2WLT42usFh977rFaXN41h81ixvl9TBZrj9xlt1j9rMLi4ilXi11f7rFZHH7T zmrx40w3i8XULx9YLFbt+sPoIODx/kYru8flvl4mjx13lzB67Jx1l91j06pONo/NS+o9tvQD eX1bVjF6fN4kF8AZxWWTkpqTWZZapG+XwJUx+VYzc8FByYpDqzeyNzD+Feli5OSQEDCRePOs jQnCFpO4cG89WxcjF4eQwFJGiS3fjzBBOM8YJS7cPMwOUiUsECdx89cKRhBbRCBU4t/F24wQ Rc2MEv3H14J1MAv0sEicWLUZrIpNwFhi8/IlbBA75CR6uyexgNi8AloS3693g8VZBFQlrn74 A7ZBVCBCYtb2H0wQNYISPybfA6vnFHCXeLTzPHMXIwfQAj2J+xe1QMLMAvISm9e8ZZ7AKDgL SccshKpZSKoWMDKvYhRNLU0uKE5KzzXSK07MLS7NS9dLzs/dxAiJvK87GJceszrEKMDBqMTD u2O1S7gQa2JZcWXuIUYJDmYlEd59Ia7hQrwpiZVVqUX58UWlOanFhxilOViUxHln7nofIiSQ nliSmp2aWpBaBJNl4uCUamD0/R7/5olLqNWCto9JxZespKrv753Cdefqr68zeh7Mb/5bk93r Y3tx7vq/G7mm6G9p6Vzyje3H/XfHtbbmfJBhdnzKVbWKW32KQOMN16vvJy2/9Nvs2ULtTYfL lZVSbTklt3xwkpnUV21dfCrvWrDqw22uTJuvTs/sOHrT8qRoWjnXvYaZ34RUlViKMxINtZiL ihMBYohblbgCAAA= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 05/24/2016 07:41 PM, Javier Martinez Canillas wrote: > The MFC IP is also inter-connected by an Async-Bridge so the CLK_ACLK333 > has to be ungated during a power domain switch. Trying to do it when the > clock is gated will fail and lead to an imprecise external abort error > when the driver tries to access the MFC registers with the PD disabled. > > For example, if the s5p-mfc module is removed and the MFC PD turned off: > > [ 186.835606] Power domain power-domain@10044060 disable failed > [ 186.835671] s5p-mfc 11000000.codec: Removing 11000000.codec > [ 186.837670] Power domain power-domain@10044060 disable failed > > And when the module is inserted again: > > [ 2395.176956] s5p_mfc_wait_for_done_dev:34: Interrupt (dev->int_type:0, command:12) timed out > [ 2395.177031] s5p_mfc_init_hw:272: Failed to load firmware > [ 2395.177384] Unhandled fault: imprecise external abort (0x1406) at 0x00000000 > [ 2395.177441] pgd = ec3b4000 > [ 2395.177467] [00000000] *pgd=00000000 > [ 2395.177507] Internal error: : 1406 [#1] PREEMPT SMP ARM > [ 2395.177550] Modules linked in: s5p_mfc mwifiex_sdio mwifiex uvcvideo s5p_jpeg v4l2_mem2mem videobuf2_vmalloc videobuf2_dma_contig videobuf2_memops videobuf2_v4l2 videobuf2_core v4l2_common videodev media [last unloaded: s5p_mfc] > [ 2395.177774] CPU: 1 PID: 2382 Comm: v4l_id Tainted: G W 4.6.0-rc6-next-20160502-00010-g7730dc64d2c1-dirty #179 > [ 2395.177857] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) > [ 2395.177906] task: ed275500 ti: e6c8c000 task.ti: e6c8c000 > [ 2395.177996] PC is at s5p_mfc_reset+0x1c4/0x284 [s5p_mfc] > [ 2395.178057] LR is at s5p_mfc_reset+0x1a4/0x284 [s5p_mfc] > > This patch fixes this issue by adding the CLK_ACLK333 as an Async-Bridge > clock for the MFC power domain, so the PD configuration works properly. > > Signed-off-by: Javier Martinez Canillas > > --- > > arch/arm/boot/dts/exynos5420.dtsi | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) Indeed patch #1 is not a hard dependency here because there are no other asb clocks. It is entirely obvious but works fine. Reviewed-by: Krzysztof Kozlowski Unless all other patches are meant to current fixes cycle (and/or cc-stable), I do not plan to apply it now. I'll take it for v4.8, because: 1. Your previous patches are needed. Without them bind/unbind won't work. 2. This is not reproducible in a regular driver operation. 3. It needs clock change to actually be useful. Is it okay? Best regards, Krzysztof > > diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi > index 4c8523471c65..f3e9d873633e 100644 > --- a/arch/arm/boot/dts/exynos5420.dtsi > +++ b/arch/arm/boot/dts/exynos5420.dtsi > @@ -313,8 +313,9 @@ > mfc_pd: power-domain@10044060 { > compatible = "samsung,exynos4210-pd"; > reg = <0x10044060 0x20>; > - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>; > - clock-names = "oscclk", "clk0"; > + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>, > + <&clock CLK_ACLK333>; > + clock-names = "oscclk", "clk0","asb0"; > #power-domain-cells = <0>; > }; > >